/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.h | 320 SmallVectorImpl<SDValue> &Results, 324 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 329 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 340 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 385 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const; 392 SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, 395 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 397 SDValue Load = 401 SDValue L [all...] |
H A D | MipsSEISelDAGToDAG.cpp | 78 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const { 207 SDValue InFlag = Node->getOperand(2); 209 SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1); 215 SDValue Ops[3] = {LHS, RHS, InFlag}; 234 SDValue CstOne = CurDAG->getTargetConstant(1, DL, MVT::i32); 236 SDValue OuFlag = CurDAG->getTargetConstant(20, DL, MVT::i32); 242 Mips::EXT, DL, MVT::i32, SDValue(DSPCtrlField, 0), OuFlag, CstOne); 244 SDValue Ops[4] = {SDValue(DSPCtrlField, 0), 246 SDValue(Carr [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreISelDAGToDAG.cpp | 49 inline SDValue getI32Imm(unsigned Imm, const SDLoc &dl) { 65 bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset); 67 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, 68 std::vector<SDValue> &OutOps) override; 87 bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base, 88 SDValue &Offset) { 111 SelectInlineAsmMemoryOperand(const SDValue [all...] |
H A D | XCoreISelLowering.cpp | 180 bool XCoreTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { 198 SDValue XCoreTargetLowering:: 199 LowerOperation(SDValue Op, SelectionDAG &DAG) const { 233 SmallVectorImpl<SDValue>&Results, 249 SDValue XCoreTargetLowering::getGlobalAddressWrapper(SDValue GA, 279 SDValue XCoreTargetLowering:: 280 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const 289 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, FoldedOffset); 293 SDValue Remainin [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonSelectionDAGInfo.cpp | 19 SDValue HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy( 20 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, 21 SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline, 25 return SDValue(); 29 return SDValue(); 61 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.h | 444 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 446 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 483 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 487 SmallVectorImpl<SDValue> &InVals) const override; 489 SDValue LowerCall(CallLoweringInfo &CLI, 490 SmallVectorImpl<SDValue> &InVals) const override; 496 SDValue LowerRetur [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCISelDAGToDAG.cpp | 47 bool SelectFrameADDR_ri(SDValue Addr, SDValue &Base, SDValue &Offset); 48 bool SelectAddrModeS9(SDValue Addr, SDValue &Base, SDValue &Offset); 49 bool SelectAddrModeImm(SDValue Addr, SDValue &Base, SDValue &Offset); 50 bool SelectAddrModeFar(SDValue Add [all...] |
H A D | ARCISelLowering.cpp | 36 static SDValue lowerCallResult(SDValue Chain, SDValue InFlag, 39 SmallVectorImpl<SDValue> &InVals); 163 SDValue ARCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 164 SDValue LHS = Op.getOperand(0); 165 SDValue RHS = Op.getOperand(1); 167 SDValue TVal = Op.getOperand(2); 168 SDValue FVa [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 234 SDValue visit(SDNode *N); 295 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 299 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 304 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 306 SDValue To[] = { Res0, Res1 }; 318 bool SimplifyDemandedBits(SDValue O [all...] |
H A D | LegalizeIntegerTypes.cpp | 40 SDValue Res = SDValue(); 212 SetPromotedInteger(SDValue(N, ResNo), Res); 215 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N, 217 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); 221 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { 223 SDValue Op = SExtPromotedInteger(N->getOperand(0)); 228 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) { 230 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 235 SDValue DAGTypeLegalize [all...] |
H A D | LegalizeVectorOps.cpp | 64 SmallDenseMap<SDValue, SDValue, 64> LegalizedNodes; 67 void AddLegalizedOperand(SDValue From, SDValue To) { 75 SDValue LegalizeOp(SDValue Op); 78 SDValue TranslateLegalizeResults(SDValue Op, SDNode *Result); 81 SDValue RecursivelyLegalizeResults(SDValue O [all...] |
H A D | LegalizeVectorTypes.cpp | 39 SDValue R = SDValue(); 181 SetScalarizedVector(SDValue(N, ResNo), R); 184 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) { 185 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 186 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 191 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) { 192 SDValue Op0 = GetScalarizedVector(N->getOperand(0)); 193 SDValue Op1 = GetScalarizedVector(N->getOperand(1)); 194 SDValue Op [all...] |
H A D | LegalizeFloatTypes.cpp | 51 SDValue R = SDValue(); 142 SetSoftenedFloat(SDValue(N, ResNo), R); 146 SDValue DAGTypeLegalizer::SoftenFloatRes_Unary(SDNode *N, RTLIB::Libcall LC) { 152 SDValue Op = GetSoftenedFloat(N->getOperand(0 + Offset)); 153 SDValue Chain = IsStrict ? N->getOperand(0) : SDValue(); 157 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, NVT, Op, 161 ReplaceValueWith(SDValue( [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 175 SDValue LanaiTargetLowering::LowerOperation(SDValue Op, 285 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops, 287 SDValue Result(nullptr, 0); 396 SDValue LanaiTargetLowering::LowerFormalArguments( 397 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 399 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 409 SDValue LanaiTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 410 SmallVectorImpl<SDValue> [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 46 bool SelectADDRrr(SDValue N, SDValue &R1, SDValue &R2); 47 bool SelectADDRri(SDValue N, SDValue &Base, SDValue &Offset); 51 bool SelectInlineAsmMemoryOperand(const SDValue &Op, 53 std::vector<SDValue> &OutOps) override; 75 bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr, 76 SDValue [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64SelectionDAGInfo.cpp | 18 SDValue AArch64SelectionDAGInfo::EmitTargetCodeForMemset( 19 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, 20 SDValue Size, Align Alignment, bool isVolatile, 50 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI); 53 return SDValue(); 62 static SDValue EmitUnrolledSetTag(SelectionDAG &DAG, const SDLoc &dl, 63 SDValue Chai [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelDAGToDAG.cpp | 36 SDValue SrcReg = CurDAG->getRegister(RISCV::X0, XLenVT); 38 SDValue SDImm = CurDAG->getTargetConstant(Inst.Imm, DL, XLenVT); 45 SrcReg = SDValue(Result, 0); 91 const SDValue ImmOp0 = CurDAG->getTargetConstant(Imm - Imm / 2, DL, VT); 92 const SDValue ImmOp1 = CurDAG->getTargetConstant(Imm / 2, DL, VT); 96 SDValue(NodeAddi0, 0), ImmOp1); 105 SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), 118 SDValue Imm = CurDAG->getTargetConstant(0, DL, XLenVT); 120 SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT); 127 SDValue Op [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 75 inline SDValue getI32Imm(unsigned Imm, const SDLoc &dl) { 82 bool isShifterOpProfitable(const SDValue &Shift, 84 bool SelectRegShifterOperand(SDValue N, SDValue &A, 85 SDValue &B, SDValue &C, 87 bool SelectImmShifterOperand(SDValue N, SDValue &A, 88 SDValue &B, bool CheckProfitability = true); 89 bool SelectShiftRegShifterOperand(SDValue [all...] |
H A D | ARMSelectionDAGInfo.cpp | 23 SDValue ARMSelectionDAGInfo::EmitSpecializedLibcall( 24 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, 25 SDValue Size, unsigned Align, RTLIB::Libcall LC) const { 33 return SDValue(); 58 return SDValue(); 122 std::pair<SDValue,SDValue> CallResult = TLI->LowerCallTo(CLI); 127 SDValue ARMSelectionDAGInf [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 55 unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) { 61 unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) { 814 SDValue AMDGPUTargetLowering::getNegatedExpression( 815 SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, 823 return SDValue(); 914 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { 1116 SDValue AMDGPUTargetLowering::LowerReturn( 1117 SDValue Chain, CallingConv::ID CallConv, 1120 const SmallVectorImpl<SDValue> &OutVals, 1143 SDValue AMDGPUTargetLowerin [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelDAGToDAG.cpp | 38 bool SelectAddr(SDNode *Op, SDValue N, SDValue &Base, SDValue &Disp); 43 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintCode, 44 std::vector<SDValue> &OutOps) override; 64 bool AVRDAGToDAGISel::SelectAddr(SDNode *Op, SDValue N, SDValue &Base, 65 SDValue &Disp) { 202 bool AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op, 204 std::vector<SDValue> [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86SelectionDAGInfo.cpp | 47 SDValue X86SelectionDAGInfo::EmitTargetCodeForMemset( 48 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Val, 49 SDValue Size, Align Alignment, bool isVolatile, 64 return SDValue(); 96 std::pair<SDValue,SDValue> CallResult = TLI.LowerCallTo(CLI); 101 return SDValue(); 105 SDValue InFla [all...] |
H A D | X86ISelDAGToDAG.cpp | 52 /// This corresponds to X86AddressMode, but uses SDValue's instead of register 61 SDValue Base_Reg; 65 SDValue IndexReg; 67 SDValue Segment; 102 void setBaseReg(SDValue Reg) { 195 bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override; 208 bool matchWrapper(SDValue N, X86ISelAddressMode &AM); 209 bool matchAddress(SDValue N, X86ISelAddressMode &AM); 210 bool matchVectorAddress(SDValue N, X86ISelAddressMode &AM); 211 bool matchAdd(SDValue [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetLowering.h | 273 SDValue Node = SDValue(); 464 virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const { 662 virtual bool hasAndNotCompare(SDValue Y) const { 669 virtual bool hasAndNot(SDValue X) const { 679 virtual bool hasBitTest(SDValue X, SDValue Y) const { return false; } 686 virtual bool shouldFoldMaskToVariableShiftPair(SDValue X) const { 721 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 169 inline SDValue getI16Imm(unsigned Imm, const SDLoc &dl) { 175 inline SDValue getI32Imm(unsigned Imm, const SDLoc &dl) { 181 inline SDValue getI64Imm(uint64_t Imm, const SDLoc &dl) { 186 inline SDValue getSmallIPtrImm(unsigned Imm, const SDLoc &dl) { 220 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, 226 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const { 242 bool SelectAddrIdx(SDValue [all...] |