Lines Matching refs:SDValue
75 inline SDValue getI32Imm(unsigned Imm, const SDLoc &dl) {
82 bool isShifterOpProfitable(const SDValue &Shift,
84 bool SelectRegShifterOperand(SDValue N, SDValue &A,
85 SDValue &B, SDValue &C,
87 bool SelectImmShifterOperand(SDValue N, SDValue &A,
88 SDValue &B, bool CheckProfitability = true);
89 bool SelectShiftRegShifterOperand(SDValue N, SDValue &A,
90 SDValue &B, SDValue &C) {
94 bool SelectShiftImmShifterOperand(SDValue N, SDValue &A,
95 SDValue &B) {
100 bool SelectAddLikeOr(SDNode *Parent, SDValue N, SDValue &Out);
102 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
103 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
105 bool SelectCMOVPred(SDValue N, SDValue &Pred, SDValue &Reg) {
112 bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
113 SDValue &Offset, SDValue &Opc);
114 bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
115 SDValue &Offset, SDValue &Opc);
116 bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
117 SDValue &Offset, SDValue &Opc);
118 bool SelectAddrOffsetNone(SDValue N, SDValue &Base);
119 bool SelectAddrMode3(SDValue N, SDValue &Base,
120 SDValue &Offset, SDValue &Opc);
121 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
122 SDValue &Offset, SDValue &Opc);
123 bool IsAddressingMode5(SDValue N, SDValue &Base, SDValue &Offset, bool FP16);
124 bool SelectAddrMode5(SDValue N, SDValue &Base, SDValue &Offset);
125 bool SelectAddrMode5FP16(SDValue N, SDValue &Base, SDValue &Offset);
126 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
127 bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
129 bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
132 bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
133 bool SelectThumbAddrModeRRSext(SDValue N, SDValue &Base, SDValue &Offset);
134 bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
135 SDValue &OffImm);
136 bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
137 SDValue &OffImm);
138 bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
139 SDValue &OffImm);
140 bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
141 SDValue &OffImm);
142 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
144 bool SelectTAddrModeImm7(SDValue N, SDValue &Base, SDValue &OffImm);
147 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
149 bool SelectT2AddrModeImm8(SDValue N, SDValue &Base, SDValue &OffImm);
150 bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
151 SDValue &OffImm);
152 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
153 SDValue &OffImm);
155 bool SelectT2AddrModeImm7Offset(SDNode *Op, SDValue N, SDValue &OffImm);
156 bool SelectT2AddrModeImm7Offset(SDNode *Op, SDValue N, SDValue &OffImm,
159 bool SelectT2AddrModeImm7(SDValue N, SDValue &Base, SDValue &OffImm);
160 bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
161 SDValue &OffReg, SDValue &ShImm);
162 bool SelectT2AddrModeExclusive(SDValue N, SDValue &Base, SDValue &OffImm);
165 bool SelectImmediateInRange(SDValue N, SDValue &OffImm);
221 SDValue PredicateMask);
224 SDValue PredicateMask, SDValue Inactive);
314 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
315 std::vector<SDValue> &OutOps) override;
318 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
319 SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
320 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
321 SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
324 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
325 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
326 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
329 SDValue GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs,
337 bool canExtractShiftFromMul(const SDValue &N, unsigned MaxShift,
338 unsigned &PowerOfTwo, SDValue &NewMulConst) const;
342 void replaceDAGValue(const SDValue &N, SDValue M);
358 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
374 static bool isScaledConstantInRange(SDValue Node, int Scale,
413 SDValue N0 = N->getOperand(0);
414 SDValue N1 = N->getOperand(1);
441 SDValue Srl = N1.getOperand(0);
449 SDValue CPTmp0;
450 SDValue CPTmp1;
451 SDValue CPTmp2;
520 bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
532 bool ARMDAGToDAGISel::canExtractShiftFromMul(const SDValue &N,
535 SDValue &NewMulConst) const {
566 void ARMDAGToDAGISel::replaceDAGValue(const SDValue &N, SDValue M) {
571 bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N,
572 SDValue &BaseReg,
573 SDValue &Opc,
582 SDValue NewMulConst;
610 bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
611 SDValue &BaseReg,
612 SDValue &ShReg,
613 SDValue &Opc,
639 bool ARMDAGToDAGISel::SelectAddLikeOr(SDNode *Parent, SDValue N, SDValue &Out) {
646 bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
647 SDValue &Base,
648 SDValue &OffImm) {
699 bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
700 SDValue &Opc) {
792 SDValue NewMulConst;
807 bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
808 SDValue &Offset, SDValue &Opc) {
843 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
844 SDValue &Offset, SDValue &Opc) {
863 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
864 SDValue &Offset, SDValue &Opc) {
883 bool ARMDAGToDAGISel::SelectAddrOffsetNone(SDValue N, SDValue &Base) {
888 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
889 SDValue &Base, SDValue &Offset,
890 SDValue &Opc) {
942 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
943 SDValue &Offset, SDValue &Opc) {
964 bool ARMDAGToDAGISel::IsAddressingMode5(SDValue N, SDValue &Base, SDValue &Offset,
1023 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
1024 SDValue &Base, SDValue &Offset) {
1028 bool ARMDAGToDAGISel::SelectAddrMode5FP16(SDValue N,
1029 SDValue &Base, SDValue &Offset) {
1033 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
1034 SDValue &Align) {
1062 bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N,
1063 SDValue &Offset) {
1076 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
1077 SDValue &Offset, SDValue &Label) {
1080 SDValue N1 = N.getOperand(1);
1094 static bool shouldUseZeroOffsetLdSt(SDValue N) {
1108 bool ARMDAGToDAGISel::SelectThumbAddrModeRRSext(SDValue N, SDValue &Base,
1109 SDValue &Offset) {
1124 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N, SDValue &Base,
1125 SDValue &Offset) {
1132 ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
1133 SDValue &Base, SDValue &OffImm) {
1170 ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1171 SDValue &OffImm) {
1176 ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1177 SDValue &OffImm) {
1182 ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1183 SDValue &OffImm) {
1187 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1188 SDValue &Base, SDValue &OffImm) {
1234 bool ARMDAGToDAGISel::SelectTAddrModeImm7(SDValue N, SDValue &Base,
1235 SDValue &OffImm) {
1261 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1262 SDValue &Base, SDValue &OffImm) {
1318 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N, SDValue &Base,
1319 SDValue &OffImm) {
1344 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1345 SDValue &Base, SDValue &OffImm) {
1371 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1372 SDValue &OffImm){
1389 bool ARMDAGToDAGISel::SelectT2AddrModeImm7(SDValue N, SDValue &Base,
1390 SDValue &OffImm) {
1417 bool ARMDAGToDAGISel::SelectT2AddrModeImm7Offset(SDNode *Op, SDValue N,
1418 SDValue &OffImm) {
1422 bool ARMDAGToDAGISel::SelectT2AddrModeImm7Offset(SDNode *Op, SDValue N,
1423 SDValue &OffImm,
1458 bool ARMDAGToDAGISel::SelectImmediateInRange(SDValue N, SDValue &OffImm) {
1467 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1468 SDValue &Base,
1469 SDValue &OffReg, SDValue &ShImm) {
1513 SDValue NewMulConst;
1527 bool ARMDAGToDAGISel::SelectT2AddrModeExclusive(SDValue N, SDValue &Base,
1528 SDValue &OffImm) {
1559 static inline SDValue getAL(SelectionDAG *CurDAG, const SDLoc &dl) {
1575 SDValue Offset, AMOpc;
1622 SDValue Chain = LD->getChain();
1623 SDValue Base = LD->getBasePtr();
1624 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG, SDLoc(N)),
1632 SDValue Chain = LD->getChain();
1633 SDValue Base = LD->getBasePtr();
1634 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG, SDLoc(N)),
1663 SDValue Chain = LD->getChain();
1664 SDValue Base = LD->getBasePtr();
1665 SDValue Ops[]= { Base, getAL(CurDAG, SDLoc(N)),
1682 SDValue Offset;
1711 SDValue Chain = LD->getChain();
1712 SDValue Base = LD->getBasePtr();
1713 SDValue Ops[]= { Base, Offset, getAL(CurDAG, SDLoc(N)),
1731 SDValue PredReg;
1732 SDValue Chain, Base, Offset;
1774 SDValue NewOffset;
1809 SDValue Ops[] = {Base, NewOffset,
1815 ReplaceUses(SDValue(N, 0), SDValue(New, 1));
1816 ReplaceUses(SDValue(N, 1), SDValue(New, 0));
1817 ReplaceUses(SDValue(N, 2), SDValue(New, 2));
1823 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
1825 SDValue RegClass =
1827 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32);
1828 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32);
1829 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1834 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1836 SDValue RegClass =
1838 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32);
1839 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32);
1840 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1845 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1847 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl,
1849 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32);
1850 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32);
1851 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1856 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1858 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl,
1860 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32);
1861 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32);
1862 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1867 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1,
1868 SDValue V2, SDValue V3) {
1870 SDValue RegClass =
1872 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32);
1873 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32);
1874 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, dl, MVT::i32);
1875 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, dl, MVT::i32);
1876 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1882 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1,
1883 SDValue V2, SDValue V3) {
1885 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl,
1887 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32);
1888 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32);
1889 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, dl, MVT::i32);
1890 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, dl, MVT::i32);
1891 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1897 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,
1898 SDValue V2, SDValue V3) {
1900 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl,
1902 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32);
1903 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32);
1904 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, dl, MVT::i32);
1905 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, dl, MVT::i32);
1906 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1914 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, const SDLoc &dl,
2050 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) {
2063 SDValue MemAddr, Align;
2070 SDValue Chain = N->getOperand(0);
2112 SDValue Pred = getAL(CurDAG, dl);
2113 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2115 SmallVector<SDValue, 7> Ops;
2124 SDValue Inc = N->getOperand(AddrOpIdx + 1);
2149 SDValue ImplDef =
2150 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
2151 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
2154 Chain = SDValue(VLdA, 2);
2157 Ops.push_back(SDValue(VLdA, 1));
2160 SDValue Inc = N->getOperand(AddrOpIdx + 1);
2166 Ops.push_back(SDValue(VLdA, 0));
2183 SDValue SuperReg = SDValue(VLd, 0);
2189 ReplaceUses(SDValue(N, Vec),
2191 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
2193 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
2205 SDValue MemAddr, Align;
2215 SDValue Chain = N->getOperand(0);
2247 SDValue Pred = getAL(CurDAG, dl);
2248 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2249 SmallVector<SDValue, 7> Ops;
2253 SDValue SrcReg;
2258 SDValue V0 = N->getOperand(Vec0Idx + 0);
2259 SDValue V1 = N->getOperand(Vec0Idx + 1);
2261 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
2263 SDValue V2 = N->getOperand(Vec0Idx + 2);
2266 SDValue V3 = (NumVecs == 3)
2267 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
2269 SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2273 SDValue Q0 = N->getOperand(Vec0Idx);
2274 SDValue Q1 = N->getOperand(Vec0Idx + 1);
2275 SrcReg = SDValue(createQRegPairNode(MVT::v4i64, Q0, Q1), 0);
2283 SDValue Inc = N->getOperand(AddrOpIdx + 1);
2314 SDValue V0 = N->getOperand(Vec0Idx + 0);
2315 SDValue V1 = N->getOperand(Vec0Idx + 1);
2316 SDValue V2 = N->getOperand(Vec0Idx + 2);
2317 SDValue V3 = (NumVecs == 3)
2318 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2320 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2324 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
2329 Chain = SDValue(VStA, 1);
2332 Ops.push_back(SDValue(VStA, 0));
2335 SDValue Inc = N->getOperand(AddrOpIdx + 1);
2359 SDValue MemAddr, Align;
2369 SDValue Chain = N->getOperand(0);
2420 SDValue Pred = getAL(CurDAG, dl);
2421 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2423 SmallVector<SDValue, 8> Ops;
2427 SDValue Inc = N->getOperand(AddrOpIdx + 1);
2433 SDValue SuperReg;
2434 SDValue V0 = N->getOperand(Vec0Idx + 0);
2435 SDValue V1 = N->getOperand(Vec0Idx + 1);
2438 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
2440 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);
2442 SDValue V2 = N->getOperand(Vec0Idx + 2);
2443 SDValue V3 = (NumVecs == 3)
2444 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2447 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2449 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2467 SuperReg = SDValue(VLdLn, 0);
2473 ReplaceUses(SDValue(N, Vec),
2475 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
2477 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
2483 SDValue PredicateMask) {
2490 SDValue PredicateMask,
2491 SDValue Inactive) {
2508 Ops.push_back(SDValue(
2515 SmallVector<SDValue, 8> Ops;
2547 ReplaceUses(SDValue(N, 0), SDValue(New, 1));
2548 ReplaceUses(SDValue(N, 1), SDValue(New, 0));
2549 ReplaceUses(SDValue(N, 2), SDValue(New, 2));
2557 SmallVector<SDValue, 8> Ops;
2590 SmallVector<SDValue, 8> Ops;
2598 SDValue CarryIn = N->getOperand(FirstInputOp + 2);
2622 SmallVector<SDValue, 8> Ops;
2639 static bool SDValueToConstBool(SDValue SDVal) {
2683 SmallVector<SDValue, 8> Ops;
2755 auto Data = SDValue(
2757 SDValue Chain = N->getOperand(0);
2760 SDValue Ops[] = {Data, N->getOperand(PtrOperand), Chain};
2763 Data = SDValue(LoadInst, 0);
2764 Chain = SDValue(LoadInst, 1);
2769 SDValue Ops[] = {Data, N->getOperand(PtrOperand), Chain};
2775 ReplaceUses(SDValue(N, i),
2777 SDValue(LoadInst, 0)));
2779 ReplaceUses(SDValue(N, i++), SDValue(LoadInst, 1));
2780 ReplaceUses(SDValue(N, i), SDValue(LoadInst, HasWriteback ? 2 : 1));
2804 SmallVector<SDValue, 8> Ops;
2807 SDValue Inactive;
2815 SDValue ImmOp = N->getOperand(OpIdx++); // step
2831 SmallVector<SDValue, 8> Ops;
2836 SDValue ImmCorpoc = N->getOperand(OpIdx++);
2843 SDValue AccLo = N->getOperand(OpIdx++);
2844 SDValue AccHi = N->getOperand(OpIdx++);
2847 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, AccLo, AccHi), 0));
2855 SDValue Imm = N->getOperand(OpIdx);
2861 SDValue Pred = getAL(CurDAG, Loc);
2862 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2869 SDValue ResultPair = SDValue(InstrNode, 0);
2880 if (SDValue(N, ResIdx).use_empty())
2882 SDValue SubReg = CurDAG->getTargetExtractSubreg(SubRegs[ResIdx], Loc,
2884 ReplaceUses(SDValue(N, ResIdx), SubReg);
2899 SDValue MemAddr, Align;
2904 SDValue Chain = N->getOperand(0);
2954 SDValue Pred = getAL(CurDAG, dl);
2955 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2959 SmallVector<SDValue, 6> Ops;
2967 SDValue Inc = N->getOperand(2);
2983 const SDValue OpsA[] = { MemAddr, Align, Pred, Reg0, Chain };
2987 Chain = SDValue(VLdA, 1);
2988 const SDValue OpsB[] = { MemAddr, Align, Pred, Reg0, Chain };
2991 SDValue ImplDef =
2992 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
2993 const SDValue OpsA[] = { MemAddr, Align, ImplDef, Pred, Reg0, Chain };
2997 SDValue SuperReg = SDValue(VLdA, 0);
2998 Chain = SDValue(VLdA, 1);
2999 const SDValue OpsB[] = { MemAddr, Align, SuperReg, Pred, Reg0, Chain };
3009 ReplaceUses(SDValue(N, 0), SDValue(VLdDup, 0));
3011 SDValue SuperReg = SDValue(VLdDup, 0);
3015 ReplaceUses(SDValue(N, Vec),
3019 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
3021 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
3057 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
3063 SDValue Ops[] = { N->getOperand(0).getOperand(0),
3072 SDValue ShOpc =
3075 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc,
3082 SDValue Ops[] = { N->getOperand(0).getOperand(0),
3105 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
3107 SDValue Ops[] = { N->getOperand(0).getOperand(0),
3127 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
3129 SDValue Ops[] = { N->getOperand(0).getOperand(0),
3148 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
3150 SDValue Ops[] = { N->getOperand(0).getOperand(0),
3172 SDValue XORSrc0 = N->getOperand(0);
3173 SDValue XORSrc1 = N->getOperand(1);
3182 SDValue ADDSrc0 = XORSrc0.getOperand(0);
3183 SDValue ADDSrc1 = XORSrc0.getOperand(1);
3184 SDValue SRASrc0 = XORSrc1.getOperand(0);
3185 SDValue SRASrc1 = XORSrc1.getOperand(1);
3214 SDValue Ops[] = {N->getOperand(1), N->getOperand(2), N->getOperand(3),
3223 ReplaceUses(SDValue(N, 0), SDValue(CmpSwap, 0));
3224 ReplaceUses(SDValue(N, 1), SDValue(CmpSwap, 2));
3247 SDValue And = N->getOperand(0);
3251 SDValue Zero = N->getOperand(1);
3255 SDValue X = And.getOperand(0);
3268 auto EmitShift = [&](unsigned Opc, SDValue Src, unsigned Imm) -> SDNode* {
3271 SDValue Ops[] = { Src, CurDAG->getTargetConstant(Imm, dl, MVT::i32),
3276 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), Src,
3302 NewN = EmitShift(ARM::tLSRri, SDValue(NewN, 0),
3331 SDValue Ptr = ST->getBasePtr();
3341 SDValue Ops[] = {ST->getValue(),
3380 SDValue CPIdx = CurDAG->getTargetConstantPool(
3386 SDValue Ops[] = {
3395 SDValue Ops[] = {
3425 SDValue TFI = CurDAG->getTargetFrameIndex(
3439 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, dl, MVT::i32),
3465 SDValue V = N->getOperand(0);
3467 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, dl, MVT::i32);
3468 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
3470 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
3474 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
3484 SDValue V = N->getOperand(0);
3486 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, dl, MVT::i32);
3487 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
3489 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
3493 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
3524 SDValue NewImm =
3532 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32),
3538 SDValue Ops[] = {N->getOperand(0), NewImm, getAL(CurDAG, dl),
3561 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3566 SDValue N2 = N0.getOperand(1);
3575 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
3577 SDValue Ops[] = { N0.getOperand(0), Imm16,
3588 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
3597 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3604 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3616 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3623 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3640 !SDValue(N, 1).use_empty())
3647 SDValue SmulLoHi = N->getOperand(1);
3648 SDValue Subc = N->getOperand(2);
3658 SDValue Ops[] = { SmulLoHi.getOperand(0), SmulLoHi.getOperand(1),
3685 SDValue Ops[] = { N->getOperand(1),
3698 SDValue Base, RegOffset, ImmOffset;
3699 const SDValue &Chain = N->getOperand(0);
3700 const SDValue &Addr = N->getOperand(1);
3710 SDValue Ops[] = {Base, RegOffset, ImmOffset, Chain};
3713 SDValue Lo = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32,
3714 SDValue(New, 0));
3715 SDValue Hi = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32,
3716 SDValue(New, 0));
3718 ReplaceUses(SDValue(N, 0), Lo);
3719 ReplaceUses(SDValue(N, 1), Hi);
3720 ReplaceUses(SDValue(N, 2), SDValue(New, 1));
3727 SDValue Base, RegOffset, ImmOffset;
3728 const SDValue &Chain = N->getOperand(0);
3729 const SDValue &Addr = N->getOperand(3);
3741 SDValue Ops[] = {SDValue(RegPair, 0), Base, RegOffset, ImmOffset, Chain};
3744 ReplaceUses(SDValue(N, 0), SDValue(New, 0));
3749 SDValue Ops[] = { N->getOperand(1),
3774 SDValue Chain = N->getOperand(0);
3775 SDValue N1 = N->getOperand(1);
3776 SDValue N2 = N->getOperand(2);
3777 SDValue N3 = N->getOperand(3);
3778 SDValue InFlag = N->getOperand(4);
3787 SDValue Int = InFlag.getOperand(0);
3792 SDValue Elements = Int.getOperand(2);
3793 SDValue Size = CurDAG->getTargetConstant(
3797 SDValue Args[] = { Elements, Size, Int.getOperand(0) };
3804 SDValue EndArgs[] = { SDValue(LoopDec, 0), N1, Chain };
3833 SDValue Tmp2 = CurDAG->getTargetConstant(CC, dl, MVT::i32);
3834 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
3837 Chain = SDValue(ResNode, 0);
3839 InFlag = SDValue(ResNode, 1);
3840 ReplaceUses(SDValue(N, 1), InFlag);
3842 ReplaceUses(SDValue(N, 0),
3843 SDValue(Chain.getNode(), Chain.getResNo()));
3853 SDValue X = N->getOperand(0);
3865 SDValue Ops[] = { X, CurDAG->getTargetConstant(Addend, dl, MVT::i32),
3871 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), X,
3878 SDValue Ops2[] = {SDValue(Add, 0), CurDAG->getConstant(0, dl, MVT::i32)};
3887 SDValue InFlag = N->getOperand(4);
3894 SDValue ARMcc = N->getOperand(2);
3907 SDValue NewARMcc = CurDAG->getConstant((unsigned)CC, dl, MVT::i32);
3908 SDValue Ops[] = {N->getOperand(0), N->getOperand(1), NewARMcc,
3935 SDValue Pred = getAL(CurDAG, dl);
3936 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
3937 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
3958 SDValue Pred = getAL(CurDAG, dl);
3959 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
3960 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
3980 SDValue Pred = getAL(CurDAG, dl);
3981 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
3982 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
4283 SDValue Chain = N->getOperand(0);
4291 SmallVector<SDValue, 5> Ops;
4315 SDValue Chain = N->getOperand(0);
4316 SDValue MemAddr = N->getOperand(2);
4333 SDValue Ops[] = {MemAddr, getAL(CurDAG, dl),
4341 SDValue OutChain = isThumb ? SDValue(Ld, 2) : SDValue(Ld, 1);
4342 if (!SDValue(N, 0).use_empty()) {
4343 SDValue Result;
4345 Result = SDValue(Ld, 0);
4347 SDValue SubRegIdx =
4350 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
4351 Result = SDValue(ResNode,0);
4353 ReplaceUses(SDValue(N, 0), Result);
4355 if (!SDValue(N, 1).use_empty()) {
4356 SDValue Result;
4358 Result = SDValue(Ld, 1);
4360 SDValue SubRegIdx =
4363 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
4364 Result = SDValue(ResNode,0);
4366 ReplaceUses(SDValue(N, 1), Result);
4368 ReplaceUses(SDValue(N, 2), OutChain);
4375 SDValue Chain = N->getOperand(0);
4376 SDValue Val0 = N->getOperand(2);
4377 SDValue Val1 = N->getOperand(3);
4378 SDValue MemAddr = N->getOperand(4);
4386 SmallVector<SDValue, 7> Ops;
4392 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0));
4749 const SDValue &Src = N->getOperand(1);
4751 SDValue Pred = getAL(CurDAG, dl);
4752 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
4753 SDValue Ops[] = { Src, Src, Pred, Reg0 };
4761 const SDValue &Src = N->getOperand(1);
4762 SDValue Pred = getAL(CurDAG, dl);
4763 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
4764 SDValue Ops[] = { Src, Pred, Reg0 };
4933 std::vector<SDValue> &Ops) {
5055 std::vector<SDValue> Ops;
5131 SDValue Ops[] = { CurDAG->getTargetConstant(SYSmValue, DL, MVT::i32),
5170 std::vector<SDValue> Ops;
5186 SDValue WriteValue[] = { N->getOperand(2), N->getOperand(3) };
5242 SDValue Ops[] = { CurDAG->getTargetConstant(SYSmValue, DL, MVT::i32),
5266 std::vector<SDValue> AsmNodeOperands;
5280 SDValue Glue = N->getGluedNode() ? N->getOperand(NumOps-1)
5281 : SDValue(nullptr,0);
5286 SDValue op = N->getOperand(i);
5304 SDValue op = N->getOperand(++i);
5326 SDValue op = N->getOperand(++i);
5342 SDValue V0 = N->getOperand(i+1);
5343 SDValue V1 = N->getOperand(i+2);
5346 SDValue PairedReg;
5356 SDValue Chain = SDValue(N,0);
5359 SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::Untyped,
5363 SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32,
5365 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32,
5367 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
5369 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
5372 std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
5379 SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];
5382 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,
5384 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
5386 SDValue Pair = SDValue(createGPRPairNode(MVT::Untyped, T0, T1), 0);
5422 SDValue New = CurDAG->getNode(N->getOpcode(), SDLoc(N),
5431 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
5432 std::vector<SDValue> &OutOps) {