Searched refs:MBBI (Results 51 - 75 of 124) sorted by relevance

12345

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp171 MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
189 MachineBasicBlock::iterator &MBBI);
484 MachineBasicBlock::iterator MBBI,
492 for (; MBBI != MBB.end(); ++MBBI) {
494 unsigned Opc = MBBI->getOpcode();
496 if (MBBI->readsRegister(Base)) {
509 MBBI->getOperand(MBBI->getDesc().getNumOperands() - 3);
514 Register InstrSrcReg = getLoadStoreRegOp(*MBBI)
483 UpdateBaseRegUses(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned Base, unsigned WordOffset, ARMCC::CondCodes Pred, unsigned PredReg) argument
1220 findIncDecBefore(MachineBasicBlock::iterator MBBI, Register Reg, ARMCC::CondCodes Pred, Register PredReg, int &Offset) argument
1240 findIncDecAfter(MachineBasicBlock::iterator MBBI, Register Reg, ARMCC::CondCodes Pred, Register PredReg, int &Offset) argument
[all...]
H A DARMFrameLowering.cpp146 bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
151 emitARMRegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
154 emitT2RegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
159 MachineBasicBlock::iterator &MBBI, const DebugLoc &dl,
164 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes,
261 MachineBasicBlock::iterator MBBI,
282 BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg)
287 BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg)
297 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
302 BuildMI(MBB, MBBI, D
145 emitRegPlusImmediate( bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, const ARMBaseInstrInfo &TII, unsigned DestReg, unsigned SrcReg, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags, ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) argument
158 emitSPUpdate(bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, const ARMBaseInstrInfo &TII, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags, ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) argument
258 emitAligningInstructions(MachineFunction &MF, ARMFunctionInfo *AFI, const TargetInstrInfo &TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, const unsigned Reg, const Align Alignment, const bool MustBeSingleInstruction) argument
338 MachineBasicBlock::iterator MBBI = MBB.begin(); local
[all...]
H A DThumb2InstrInfo.cpp71 MachineBasicBlock::iterator MBBI = Tail; local
74 --MBBI;
83 while (Count && MBBI != E) {
84 if (MBBI->isDebugInstr()) {
85 --MBBI;
88 if (MBBI->getOpcode() == ARM::t2IT) {
89 unsigned Mask = MBBI->getOperand(1).getImm();
91 MBBI->eraseFromParent();
95 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
99 --MBBI;
230 emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
[all...]
H A DThumbRegisterInfo.h40 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrInfo.h117 MachineBasicBlock::iterator MBBI,
121 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
125 MachineBasicBlock::iterator MBBI,
129 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
H A DMips16InstrInfo.h56 MachineBasicBlock::iterator MBBI,
63 MachineBasicBlock::iterator MBBI,
H A DMipsExpandPseudo.cpp54 MachineBasicBlock::iterator MBBI,
57 MachineBasicBlock::iterator MBBI,
67 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
817 MachineBasicBlock::iterator MBBI,
822 switch (MBBI->getOpcode()) {
825 return expandAtomicCmpSwap(MBB, MBBI, NMBB);
828 return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB);
851 return expandAtomicBinOpSubword(MBB, MBBI, NMBB);
863 return expandAtomicBinOp(MBB, MBBI, NMBB, 4);
875 return expandAtomicBinOp(MBB, MBBI, NMB
816 expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NMBB) argument
884 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86PadShortFunction.cpp82 MachineBasicBlock::iterator &MBBI,
221 /// just prior to the return at MBBI
223 MachineBasicBlock::iterator &MBBI,
225 DebugLoc DL = MBBI->getDebugLoc();
229 BuildMI(*MBB, MBBI, DL, TSM.getInstrInfo()->get(X86::NOOP));
222 addPadding(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI, unsigned int NOOPsToAdd) argument
H A DX86CondBrFolding.cpp200 auto MBBI = std::find(MBB->succ_begin(), MBB->succ_end(), SuccMBB); local
201 if (MBBI == MBB->succ_end())
203 MBB->setSuccProbability(MBBI, Prob);
424 for (auto MBBI : RemoveList) {
425 while (!MBBI->succ_empty())
426 MBBI->removeSuccessor(MBBI->succ_end() - 1);
428 MBBI->eraseFromParent();
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp89 MachineBasicBlock::iterator MBBI);
481 MachineBasicBlock::iterator MBBI)
484 if (MBBI == MBB.begin())
487 // assert that MBBI is a "restore %g0, %g0, %g0".
488 assert(MBBI->getOpcode() == SP::RESTORErr
489 && MBBI->getOperand(0).getReg() == SP::G0
490 && MBBI->getOperand(1).getReg() == SP::G0
491 && MBBI->getOperand(2).getReg() == SP::G0);
493 MachineBasicBlock::iterator PrevInst = std::prev(MBBI);
504 case SP::ADDri: return combineRestoreADD(MBBI, PrevIns
480 tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) argument
[all...]
H A DSparcInstrInfo.h88 MachineBasicBlock::iterator MBBI,
94 MachineBasicBlock::iterator MBBI,
H A DSparcFrameLowering.h60 MachineBasicBlock::iterator MBBI,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineFunction.cpp309 MachineFunction::iterator MBBI, E = end(); local
311 MBBI = begin();
313 MBBI = MBB->getIterator();
317 if (MBBI != begin())
318 BlockNo = std::prev(MBBI)->getNumber() + 1;
320 for (; MBBI != E; ++MBBI, ++BlockNo) {
321 if (MBBI->getNumber() != (int)BlockNo) {
323 if (MBBI->getNumber() != -1) {
324 assert(MBBNumbering[MBBI
[all...]
H A DRegisterScavenging.cpp95 MBBI = std::prev(MBB.end());
113 MachineInstr &MI = *MBBI;
160 MachineInstr &MI = *MBBI;
169 if (MBBI == MBB->begin()) {
170 MBBI = MachineBasicBlock::iterator(nullptr);
173 --MBBI;
179 MBBI = MBB->begin();
182 assert(MBBI != MBB->end() && "Already past the end of the basic block!");
183 MBBI = std::next(MBBI);
[all...]
H A DVirtRegMap.cpp287 for (SlotIndexes::MBBIndexIterator MBBI = Indexes->findMBBIndex(First);
288 MBBI != Indexes->MBBIndexEnd() && MBBI->first <= Last; ++MBBI) {
289 SlotIndex MBBBegin = MBBI->first;
305 MachineBasicBlock *MBB = MBBI->second;
499 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
500 MBBI != MBBE; ++MBBI) {
501 LLVM_DEBUG(MBBI
[all...]
H A DCFIInstrInserter.cpp303 auto MBBI = MBBInfo.MBB->begin(); local
304 DebugLoc DL = MBBInfo.MBB->findDebugLoc(MBBI);
319 BuildMI(*MBBInfo.MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
328 BuildMI(*MBBInfo.MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
336 BuildMI(*MBBInfo.MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
343 *MBBInfo.MBB, MBBI);
354 BuildMI(*MBBInfo.MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
375 BuildMI(*MBBInfo.MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
H A DLiveDebugVariables.cpp696 for (MachineBasicBlock::iterator MBBI = MBB->begin(), MBBE = MBB->end();
697 MBBI != MBBE;) {
700 if (!MBBI->isDebugInstr()) {
701 ++MBBI;
707 MBBI == MBB->begin()
709 : LIS->getInstructionIndex(*std::prev(MBBI)).getRegSlot();
714 if ((MBBI->isDebugValue() && handleDebugValue(*MBBI, Idx)) ||
715 (MBBI->isDebugLabel() && handleDebugLabel(*MBBI, Id
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFrameLowering.cpp642 MachineBasicBlock::iterator MBBI,
665 LiveRegs.stepBackward(*MBBI);
677 BuildMI(MBB, MBBI, DL, TII->get(OrSaveExec), ScratchExecCopy).addImm(-1);
702 MachineBasicBlock::iterator MBBI = MBB.begin(); local
733 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), FuncInfo->SGPRForFPSaveRestoreCopy)
740 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY),
770 ScratchExecCopy = buildScratchExecCopy(LiveRegs, MF, MBB, MBBI, true);
772 buildPrologSpill(LiveRegs, MBB, MBBI, TII, Reg.VGPR,
782 ScratchExecCopy = buildScratchExecCopy(LiveRegs, MF, MBB, MBBI, true);
787 BuildMI(MBB, MBBI, D
639 buildScratchExecCopy(LivePhysRegs &LiveRegs, MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, bool IsProlog) argument
937 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator(); local
[all...]
H A DSIPreEmitPeephole.cpp308 for (MachineBasicBlock::iterator MBBI = MBB.begin(); MBBI != MBBE; ) {
309 MachineInstr &MI = *MBBI;
310 ++MBBI;
H A DSILoadStoreOptimizer.cpp891 MachineBasicBlock::iterator MBBI = std::next(CI.I); local
893 for (; MBBI != E; ++MBBI) {
895 if (MBBI == MBBE) {
905 if ((getInstClass(MBBI->getOpcode(), *TII) != InstClass) ||
906 (getInstSubclass(MBBI->getOpcode(), *TII) != InstSubclass)) {
909 // 1. It is safe to move I down past MBBI.
910 // 2. It is safe to move MBBI down past the instruction that I will
913 if (MBBI->hasUnmodeledSideEffects()) {
919 if (MBBI
1647 MachineBasicBlock::iterator MBBI = MI.getIterator(); local
1865 MachineBasicBlock::iterator MBBI = MI.getIterator(); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64A53Fix835769.cpp133 MachineFunction::iterator MBBI(MBB);
136 if (MBBI == MBB->getParent()->begin())
142 MachineBasicBlock *PrevBB = &*std::prev(MBBI);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZFrameLowering.h34 MachineBasicBlock::iterator MBBI,
H A DSystemZInstrInfo.cpp241 // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
247 MachineBasicBlock::iterator MBBI,
262 return BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
266 return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
768 MachineBasicBlock::iterator MBBI,
775 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
777 MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
779 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
781 MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
787 emitGRX32Move(MBB, MBBI, D
246 emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, unsigned LowLowOpcode, unsigned Size, bool KillSrc, bool UndefSrc) const argument
767 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const argument
859 storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
874 loadRegFromStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
1918 loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned Reg, uint64_t Value) const argument
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineFunction.h720 void insert(iterator MBBI, MachineBasicBlock *MBB) {
721 BasicBlocks.insert(MBBI, MBB);
723 void splice(iterator InsertPt, iterator MBBI) {
724 BasicBlocks.splice(InsertPt, BasicBlocks, MBBI);
729 void splice(iterator InsertPt, iterator MBBI, iterator MBBE) {
730 BasicBlocks.splice(InsertPt, BasicBlocks, MBBI, MBBE);
733 void remove(iterator MBBI) { BasicBlocks.remove(MBBI); }
734 void remove(MachineBasicBlock *MBBI) { BasicBlocks.remove(MBBI); }
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFrameLowering.h72 void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,

Completed in 392 milliseconds

12345