/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | Utils.cpp | 493 uint64_t Imm, 503 return C1.trunc(Imm).sext(C1.getBitWidth()); 492 ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI) argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsTargetStreamer.cpp | 188 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, argument 190 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI); 240 int16_t Imm, SMLoc IDLoc, 242 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI); 239 emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64InstPrinter.h | 63 void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SILowerI1Copies.cpp | 763 int64_t Imm = MI->getOperand(1).getImm(); 764 if (Imm == 0) { 768 if (Imm == -1) {
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H A D | R600InstrInfo.cpp | 1367 uint64_t Imm) const { 1370 setImmOperand(*MovImm, R600::OpName::literal, Imm); 1389 int64_t Imm) const { 1393 MI.getOperand(Idx).setImm(Imm);
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H A D | R600ControlFlowFinalizer.cpp | 370 int64_t Imm = Src.second; local 373 return val->isImm() && (val->getImm() == Imm);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 324 bool RISCVTargetLowering::isLegalICmpImmediate(int64_t Imm) const { 325 return isInt<12>(Imm); 328 bool RISCVTargetLowering::isLegalAddImmediate(int64_t Imm) const { 329 return isInt<12>(Imm); 370 bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, argument 376 if (Imm.isNegZero()) 378 return Imm.isZero(); 3007 int64_t Imm = ConstNode->getSExtValue(); 3008 if (isPowerOf2_64(Imm + 1) || isPowerOf2_64(Imm [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 3675 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, argument 3690 if (Imm == 0) 3694 APInt ImmVal = Imm; 3696 ImmVal = Imm.sext(alignTo(BitSize, 64)); 3710 int X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, argument 3740 if (Idx == 1 && Imm.getBitWidth() == 64) { 3741 uint64_t ImmVal = Imm.getZExtValue(); 3751 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 3758 if (Idx == 1 && Imm 3807 getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) argument [all...] |
H A D | X86FrameLowering.cpp | 104 static unsigned getSUBriOpcode(bool IsLP64, int64_t Imm) { argument 106 if (isInt<8>(Imm)) 110 if (isInt<8>(Imm)) 116 static unsigned getADDriOpcode(bool IsLP64, int64_t Imm) { argument 118 if (isInt<8>(Imm)) 122 if (isInt<8>(Imm)) 136 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) { argument 138 if (isInt<8>(Imm)) 142 if (isInt<8>(Imm))
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
H A D | SparcAsmParser.cpp | 250 struct ImmOp Imm; member in union:__anon4304::SparcOperand::__anon4305 294 return Imm.Val; 325 case k_Immediate: OS << "Imm: " << getImm() << "\n"; break; 402 Op->Imm.Val = Val; 497 const MCExpr *Imm = Op->getImm(); local 501 Op->Mem.Off = Imm;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 6622 unsigned OpCmode, Imm; local 6640 Imm = SplatBits; 6650 Imm = SplatBits; 6656 Imm = SplatBits >> 8; 6670 Imm = SplatBits; 6676 Imm = SplatBits >> 8; 6682 Imm = SplatBits >> 16; 6688 Imm = SplatBits >> 24; 6699 Imm = SplatBits >> 8; 6711 Imm 6880 isSingletonVEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) argument 6908 isVEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseVEXT, unsigned &Imm) argument 7947 unsigned Imm, WhichResult; local 8293 unsigned Imm = 0; local 14266 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); local 15511 SearchLoopIntrinsic(SDValue N, ISD::CondCode &CC, int &Imm, bool &Negate) argument 15565 int Imm = 1; local 17934 isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const argument 18121 shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
H A D | LoopStrengthReduce.cpp | 3830 int64_t Imm = ExtractImmediate(G, SE); local 3831 if (G->isZero() || Imm == 0) 3834 F.BaseOffset = (uint64_t)F.BaseOffset + Imm; 4075 int64_t Imm; member in struct:__anon4672::WorkItem 4079 : LUIdx(LI), Imm(I), OrigReg(R) {} 4090 << " , add offset " << Imm; local 4109 int64_t Imm = ExtractImmediate(Reg, SE); local 4113 Pair.first->second.insert(std::make_pair(Imm, Use)); 4168 int64_t Imm = (uint64_t)JImm - M->first; local 4171 if (UniqueItems.insert(std::make_pair(LUIdx, Imm)) 4186 int64_t Imm = WI.Imm; local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGISel.cpp | 3255 SDValue Imm = RecordedNodes[RecNo].first; 3257 if (Imm->getOpcode() == ISD::Constant) { 3258 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue(); 3259 Imm = CurDAG->getTargetConstant(*Val, SDLoc(NodeToMatch), 3260 Imm.getValueType()); 3261 } else if (Imm->getOpcode() == ISD::ConstantFP) { 3262 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 3263 Imm = CurDAG->getTargetConstantFP(*Val, SDLoc(NodeToMatch), 3264 Imm.getValueType()); 3267 RecordedNodes.push_back(std::make_pair(Imm, RecordedNode [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 527 // Returns true and sets Imm if: 534 static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) { argument 548 Imm = SplatValue; 1464 unsigned Opc, SDValue Imm, 1473 if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) { 1496 Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm); 1498 Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG); 2586 APInt Imm(32, 0); 2593 Imm << 1463 lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc, SDValue Imm, bool BigEndian) argument 3517 unsigned Imm = MMO.getOffset(); local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 138 inline SDValue getImm(const SDNode *Node, uint64_t Imm) const { 139 return CurDAG->getTargetConstant(Imm, SDLoc(Node), Node->getValueType(0)); 1601 APFloat Imm = cast<ConstantFPSDNode>(Node)->getValueAPF(); local 1602 if (Imm.isZero() || Imm.isNegZero()) 1604 SystemZVectorConstantInfo VCI(Imm);
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | InstructionSelectorImpl.h | 276 llvm_unreachable("Expected Imm or CImm operand"); 298 llvm_unreachable("Expected Imm or CImm operand"); 904 int64_t Imm = MatchTable[CurrentIdx++]; local 906 OutMIs[InsnID].addImm(Imm); 909 << "], " << Imm << ")\n"); local 949 llvm_unreachable("Expected Imm or CImm operand");
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/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | AsmWriterEmitter.cpp | 931 auto Imm = CGA.ResultOperands[i].getImm(); local 932 int32_t Imm32 = int32_t(Imm); 933 if (Imm != Imm32)
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64AsmPrinter.cpp | 1034 int64_t Imm = MI->getOperand(0).getImm(); local 1035 if ((Imm & 32) && (Imm & 6)) {
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H A D | AArch64ISelLowering.cpp | 1100 static bool optimizeLogicalImm(SDValue Op, unsigned Size, uint64_t Imm, argument 1104 uint64_t OldImm = Imm, NewImm, Enc; 1109 if (Imm == 0 || Imm == Mask || 1110 AArch64_AM::isLogicalImmediate(Imm & Mask, Size)) 1117 Imm &= DemandedBits; 1128 uint64_t InvertedImm = ~Imm & DemandedBits; 1135 NewImm = (Imm | Ones) & Mask; 1149 uint64_t Hi = Imm >> EltSize, DemandedBitsHi = DemandedBits >> EltSize; 1151 // Return if there is mismatch in any of the demanded bits of Imm an 6428 isFPImmLegal(const APFloat &Imm, EVT VT, bool OptForSize) const argument 7105 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1); local 7183 isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) argument 7214 isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT, unsigned &Imm) argument 7545 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS); local 7739 unsigned Imm; local 10354 shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const argument 11798 SDValue Imm; local [all...] |
H A D | AArch64ISelLowering.h | 471 bool isFPImmLegal(const APFloat &Imm, EVT VT, 564 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.cpp | 1419 // Subroutine to determine if we can use the Imm as part of d-form. 1420 auto CanUseDForm = [](int64_t Imm) { return isInt<16>(Imm) && Imm % 4 == 0; }; 1421 // Subroutine to materialize the Imm into TempReg. 1423 MachineBasicBlock::iterator MBBI, int64_t Imm, 1425 assert(isInt<32>(Imm) && "Unhandled imm"); 1426 if (isInt<16>(Imm)) 1428 .addImm(Imm); 1431 .addImm(Imm >> 1 [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64InstructionSelector.cpp | 1395 int64_t Imm = *ShiftImm; 1396 if (Imm < 0) 1403 if (Imm > 7) 1407 if (Imm > 15) 1411 if (Imm > 31) 1415 if (Imm > 63) 1419 return Imm; 2288 int64_t Imm = *COff; local 2291 if ((Imm & (Size - 1)) == 0 && Imm > 3920 int Imm = DefSize == 32 ? AArch64_AM::getFP32Imm(ImmValAPF) local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.h | 296 bool isFPImmLegal(const APFloat &Imm, EVT VT, 303 bool isLegalICmpImmediate(int64_t Imm) const override;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/ObjectYAML/ |
H A D | MachOEmitter.cpp | 400 uint8_t OpByte = Opcode.Opcode | Opcode.Imm; 505 uint8_t OpByte = Opcode.Opcode | Opcode.Imm;
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H A D | MachOYAML.cpp | 169 IO.mapRequired("Imm", RebaseOpcode.Imm); 176 IO.mapRequired("Imm", BindOpcode.Imm);
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