Searched refs:Imm (Results 151 - 175 of 244) sorted by relevance

12345678910

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp415 struct ImmOp Imm; member in union:__anon3880::AArch64Operand::__anon3881
444 Imm = o.Imm;
505 return Imm.Val;
1398 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1414 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1738 unsigned Imm = local
1740 Inst.addOperand(MCOperand::createImm(Imm));
1747 unsigned Imm = AArch64_AM::getArithExtendImm(ET, getShiftExtendAmount()); local
1748 Inst.addOperand(MCOperand::createImm(Imm));
1755 unsigned Imm = AArch64_AM::getArithExtendImm(ET, getShiftExtendAmount()); local
2638 const MCExpr *Imm = nullptr; local
3714 uint64_t Imm = (cast<MCConstantExpr>(SubExprVal))->getValue(); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp868 unsigned Imm; member in struct:__anon4036::ARMOperand::ShifterImmOp
885 unsigned Imm; member in struct:__anon4036::ARMOperand::RotImmOp
914 struct ImmOp Imm; member in union:__anon4036::ARMOperand::__anon4039
980 return Imm.Val;
985 return Imm.Val;
1057 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1058 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1072 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1073 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1087 if (isa<MCSymbolRefExpr>(Imm
2495 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); local
2702 unsigned Imm = CE->getValue(); local
2803 int32_t Imm = Memory.OffsetImm->getValue(); local
3160 int Imm = CE->getValue(); local
3171 int Imm = CE->getValue(); local
3191 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, local
3419 unsigned Imm = 0; local
3441 unsigned Imm = CE->getValue(); local
3551 CreateShifterImm(bool isASR, unsigned Imm, SMLoc S, SMLoc E) argument
3561 CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) argument
4053 int64_t Imm = 0; local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp263 APInt Imm(64, MO.getImm());
269 return MachineOperand::CreateImm(Imm.getLoBits(32).getSExtValue());
271 return MachineOperand::CreateImm(Imm.getHiBits(32).getSExtValue());
1948 // The AMDGPU backend only supports Imm operands and not CImm or FPImm.
1950 const APInt &Imm = ImmOp.getFPImm()->getValueAPF().bitcastToAPInt(); local
1951 ImmOp.ChangeToImmediate(Imm.getZExtValue());
1981 APInt Imm(Size, I.getOperand(1).getImm());
1984 if (IsSgpr && TII.isInlineConstant(Imm)) {
1994 .addImm(Imm.trunc(32).getZExtValue());
1997 .addImm(Imm
[all...]
H A DSIInstrInfo.cpp1624 APInt Imm(64, SrcOp.getImm());
1626 .addImm(Imm.getLoBits(32).getZExtValue())
1629 .addImm(Imm.getHiBits(32).getZExtValue())
1796 APInt Imm(64, SrcOp.getImm());
1797 Imm.ashrInPlace(Part * 32);
1798 MovDPP.addImm(Imm.getLoBits(32).getZExtValue());
2562 APInt Imm(32, ImmOp->getImm());
2565 Imm = Imm.ashr(16);
2568 if (!isInlineConstant(Imm))
2638 const int64_t Imm = ImmOp->getImm(); local
2721 const int64_t Imm = ImmOp->getImm(); local
3868 uint64_t Imm = Op->getImm(); local
5452 uint32_t Imm = OffsetWidthOp.getImm(); local
6043 uint32_t Imm = Inst.getOperand(2).getImm(); local
[all...]
H A DSIInsertWaitcnts.cpp1086 int64_t Imm = II->getOperand(0).getImm();
1087 ScoreBrackets.applyWaitcnt(AMDGPU::decodeWaitcnt(IV, Imm));
1282 int Imm = TII->getNamedOperand(Inst, AMDGPU::OpName::tgt)->getImm();
1283 if (Imm >= 32 && Imm <= 63)
1285 else if (Imm >= 12 && Imm <= 15)
H A DSIInstrInfo.h704 bool isInlineConstant(const APInt &Imm) const;
706 bool isInlineConstant(const APFloat &Imm) const {
707 return isInlineConstant(Imm.bitcastToAPInt());
1014 static bool isLegalMUBUFImmOffset(unsigned Imm) { argument
1015 return isUInt<12>(Imm);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp685 int Imm = MBBI->getOperand(ImmIdx).getImm(); local
694 Imm = -Imm;
702 .addImm(Imm * 8)
707 Imm = -Imm;
714 .addImm(Imm * 8)
720 .addImm(Imm * 8)
725 Imm = -Imm;
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h433 bool isFPImmLegal(const APFloat &Imm, EVT VT,
436 bool isLegalICmpImmediate(int64_t Imm) const override;
437 bool isLegalAddImmediate(int64_t Imm) const override;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.cpp779 int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm()); local
780 int Offset = FIOffset + Imm;
781 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp476 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2); local
478 std::make_pair(PltSectionVA + Byte, GotPltSectionVA + Imm));
483 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2); local
484 Result.push_back(std::make_pair(PltSectionVA + Byte, Imm));
501 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2); local
503 std::make_pair(PltSectionVA + Byte, PltSectionVA + Byte + 6 + Imm));
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp293 int64_t Imm = Inst.getOperand(0).getImm();
294 Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsTargetStreamer.h126 void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc,
136 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
H A DMipsISelLowering.cpp4306 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, argument
4310 if (Imm.isNegZero())
4312 return Imm.isZero();
4756 unsigned Imm = MI.getOperand(2).getImm(); local
4766 .addImm(Imm);
4778 .addImm(Imm + (IsLittle ? 0 : 3))
4783 .addImm(Imm + (IsLittle ? 3 : 0))
4802 unsigned Imm = MI.getOperand(2).getImm(); local
4813 .addImm(Imm);
4822 .addImm(Imm
4886 unsigned Imm = MI.getOperand(2).getImm(); local
4936 unsigned Imm = MI.getOperand(2).getImm(); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/ObjectYAML/
H A DMachOYAML.h93 uint8_t Imm; member in struct:llvm::MachOYAML::RebaseOpcode
99 uint8_t Imm; member in struct:llvm::MachOYAML::BindOpcode
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCSEInfo.cpp339 GISelInstProfileBuilder::addNodeIDImmediate(int64_t Imm) const {
340 ID.AddInteger(Imm);
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h49 int64_t Imm; member in struct:llvm::PtrAddChain
H A DMachineIRBuilder.h123 int64_t Imm; member in union:llvm::SrcOp::__anon3152
137 SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
138 SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
152 MIB.addImm(Imm);
195 return Imm;
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h78 int64_t Imm; member in struct:llvm::RegImmPair
80 RegImmPair(Register Reg, int64_t Imm) : Reg(Reg), Imm(Imm) {} argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h429 bool isLegalICmpImmediate(int64_t Imm) const override;
435 bool isLegalAddImmediate(int64_t Imm) const override;
546 bool isFPImmLegal(const APFloat &Imm, EVT VT,
556 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
H A DARMISelDAGToDAG.cpp75 inline SDValue getI32Imm(unsigned Imm, const SDLoc &dl) { argument
76 return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
167 inline bool is_so_imm(unsigned Imm) const {
168 return ARM_AM::getSOImmVal(Imm) != -1;
171 inline bool is_so_imm_not(unsigned Imm) const {
172 return ARM_AM::getSOImmVal(~Imm) != -1;
175 inline bool is_t2_so_imm(unsigned Imm) const {
176 return ARM_AM::getT2SOImmVal(Imm) != -1;
179 inline bool is_t2_so_imm_not(unsigned Imm) const {
180 return ARM_AM::getT2SOImmVal(~Imm) !
348 isInt32Immediate(SDNode *N, unsigned &Imm) argument
358 isInt32Immediate(SDValue N, unsigned &Imm) argument
365 isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) argument
2855 SDValue Imm = N->getOperand(OpIdx); local
3511 uint32_t Imm = (uint32_t) N1C->getZExtValue(); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInst.h153 bool evaluateAsConstantImm(int64_t &Imm) const;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp461 unsigned Imm = createResultReg(&WebAssembly::I32RegClass); local
463 TII.get(WebAssembly::CONST_I32), Imm)
470 .addReg(Imm);
491 unsigned Imm = createResultReg(&WebAssembly::I32RegClass); local
493 TII.get(WebAssembly::CONST_I32), Imm)
500 .addReg(Imm);
506 .addReg(Imm);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBTFDebug.cpp1197 uint32_t Imm; local
1200 Imm = PatchImms[GVar];
1206 OutMI.addOperand(MCOperand::createImm(Imm));
1218 uint32_t Imm = PatchImms[GVar]; local
1225 OutMI.addOperand(MCOperand::createImm(Imm));
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp1428 int64_t Imm;
1429 if (checkForImmediate(*InitVal, Imm))
1430 return (EndVal->getImm() == Imm);
1597 static bool isImmValidForOpcode(unsigned CmpOpc, int64_t Imm) { argument
1600 return isUInt<8>(Imm);
1602 return isInt<8>(Imm);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/
H A DMachO_arm64.cpp564 uint32_t Imm = (static_cast<uint32_t>(Value) & ((1 << 28) - 1)) >> 2; local
565 uint32_t FixedInstr = RawInstr | Imm;

Completed in 343 milliseconds

12345678910