Searched refs:Def (Results 51 - 75 of 182) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DSplitKit.cpp429 SlotIndex Def = VNI->def; local
436 VNInfo *PV = PS.getVNInfoAt(Def);
437 if (PV != nullptr && PV->def == Def)
438 S.createDeadDef(Def, LIS.getVNInfoAllocator());
444 const MachineInstr *DefMI = LIS.getInstructionFromIndex(Def);
460 S.createDeadDef(Def, LIS.getVNInfoAllocator());
522 unsigned SubIdx, LiveInterval &DestLI, bool Late, SlotIndex Def) {
524 bool FirstCopy = !Def.isValid();
533 Def = Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot();
539 [Def,
520 buildSingleSubRegCopy(unsigned FromReg, unsigned ToReg, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, unsigned SubIdx, LiveInterval &DestLI, bool Late, SlotIndex Def) argument
597 SlotIndex Def = buildSingleSubRegCopy(FromReg, ToReg, MBB, InsertBefore, local
640 SlotIndex Def; local
862 SlotIndex Def = Copies[i]->def; local
1238 removeDeadSegment(SlotIndex Def, LiveRange &LR) argument
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H A DMachineLICM.cpp200 unsigned Def; member in struct:__anon3512::MachineLICMBase::CandidateInfo
204 : MI(mi), Def(def), FI(fi) {}
209 void HoistPostRA(MachineInstr *MI, unsigned Def);
440 unsigned Def = 0; local
489 if (Def)
492 Def = Reg;
514 if (Def && !RuledOut) {
518 Candidates.push_back(CandidateInfo(MI, Def, FI));
585 unsigned Def = Candidate.Def; local
625 HoistPostRA(MachineInstr *MI, unsigned Def) argument
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H A DRegisterPressure.cpp772 for (const RegisterMaskPair &Def : RegOpers.Defs) {
773 unsigned Reg = Def.RegUnit;
775 LaneBitmask PreviousMask = LiveRegs.erase(Def);
776 LaneBitmask NewMask = PreviousMask & ~Def.LaneMask;
778 LaneBitmask LiveOut = Def.LaneMask & ~PreviousMask;
842 for (const RegisterMaskPair &Def : RegOpers.Defs) {
843 unsigned RegUnit = Def.RegUnit;
845 (LiveRegs.contains(RegUnit) & Def.LaneMask).none())
933 for (const RegisterMaskPair &Def : RegOpers.Defs) {
934 LaneBitmask PreviousMask = LiveRegs.insert(Def);
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H A DRegisterCoalescer.cpp2470 SlotIndex Def = VNI->def; local
2471 MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
2483 LiveQueryResult LRQ = LI.Query(Def);
2494 LiveQueryResult LRQ = S.Query(Def);
2985 SlotIndex Def = LR.getValNumInfo(i)->def; local
2991 LIS->pruneValue(Other.LR, Def, &EndPoints);
2999 if (!Def.isBlock()) {
3005 Indexes->getInstructionFromIndex(Def)->operands()) {
3014 // the live range also reaches the instruction at Def.
3016 EndPoints.push_back(Def);
3092 SlotIndex Def = LR.getValNumInfo(i)->def; local
3140 isDefInSubRange(LiveInterval &LI, SlotIndex Def) argument
3181 SlotIndex Def = VNI->def; local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DRewriteStatepointsForGC.cpp400 /// instruction 'Def' is an input to 'Def' whose base is also a base of 'Def'.
403 /// defining value. The 'base defining value' for 'Def' is the transitive
526 Value *Def = CI->stripPointerCasts(); local
529 assert(cast<PointerType>(Def->getType())->getAddressSpace() ==
535 assert(!isa<CastInst>(Def) && "shouldn't find another cast here");
536 return findBaseDefiningValue(Def);
631 Value *Def = findBaseDefiningValueCached(I, Cache); local
632 auto Found = Cache.find(Def);
779 Value *Def = findBaseOrBDV(I, Cache); local
1827 Value *Def = Pair.first; local
1858 Value *Def = Pair.first; local
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H A DNewGVN.cpp2884 for (const auto &Def : *MemoryBlockDefs) {
2885 MemoryAccessToClass[&Def] = TOPClass;
2886 auto *MD = dyn_cast<MemoryDef>(&Def);
2889 const MemoryPhi *MP = cast<MemoryPhi>(&Def);
3507 // Only one of Def and U will be set.
3508 // The bool in the Def tells us whether the Def is the stored value of a
3510 PointerIntPair<Value *, 1, bool> Def;
3552 return std::tie(DFSIn, DFSOut, LocalNum, Def, U) <
3553 std::tie(Other.DFSIn, Other.DFSOut, Other.LocalNum, Other.Def,
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H A DGVNHoist.cpp384 // Return true when there are memory uses of Def in BB.
385 bool hasMemoryUse(const Instruction *NewPt, MemoryDef *Def, argument
391 Instruction *OldPt = Def->getMemoryInst();
400 // Do not check whether MU aliases Def when MU occurs after OldPt.
404 // Do not check whether MU aliases Def when MU occurs before NewPt.
412 if (MemorySSAUtil::defClobbersUseOrDef(Def, MU, *AA))
438 // Return true when there are exception handling or loads of memory Def
439 // between Def and NewPt. This function is only called for stores: Def is
445 bool hasEHOrLoadsOnPath(const Instruction *NewPt, MemoryDef *Def, argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRegBankReassign.cpp417 MachineBasicBlock::const_instr_iterator Def(MI.getIterator());
419 for (unsigned S = StallCycles; S && Def != B && Defs != 3; --S) {
422 --Def;
423 if (Def->getOpcode() == TargetOpcode::IMPLICIT_DEF)
425 if (Def->modifiesRegister(Reg1, TRI))
427 if (Def->modifiesRegister(Reg2, TRI))
437 const MachineInstr *Def = MRI->getUniqueVRegDef(Reg);
441 if (Def && Def->isCopy() && Def
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H A DGCNDPPCombine.cpp143 auto *Def = getVRegSubRegDef(getRegSubRegPair(OldOpnd), *MRI); local
144 if (!Def)
147 switch(Def->getOpcode()) {
153 auto &Op1 = Def->getOperand(1);
190 auto *Def = getVRegSubRegDef(CombOldVGPR, *MRI); local
191 DPPInst.addReg(CombOldVGPR.Reg, Def ? 0 : RegState::Undef,
H A DGCNHazardRecognizer.h82 int checkVALUHazardsHelper(const MachineOperand &Def, const MachineRegisterInfo &MRI);
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenDAGPatterns.h451 Record *Def; member in class:llvm::SDNodeInfo
467 Record *getRecord() const { return Def; }
1064 Predicate(Record *R, bool C = true) : Def(R), IfCond(C), IsHwMode(false) {
1069 Predicate(StringRef FS, bool C = true) : Def(nullptr), Features(FS.str()),
1080 : std::string(Def->getValueAsString("CondString"));
1087 return IfCond == P.IfCond && IsHwMode == P.IsHwMode && Def == P.Def;
1092 assert(!Def == !P.Def && "Inconsistency between Def an
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H A DCodeGenRegisters.cpp618 void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) override {
619 std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices");
621 ListInit *SubRegs = Def->getValueAsListInit("SubRegs");
623 PrintFatalError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch");
625 PrintFatalError(Def->getLoc(),
632 ST.evaluate(SubRegs->getElement(i), Lists[i], Def->getLoc());
640 Record *RegisterCl = Def->getRecords().getClass("Register");
643 Def->getValueAsListOfStrings("RegAsmNames");
663 PrintFatalError(Def->getLoc(),
673 std::make_unique<Record>(Name, Def
1227 getSubRegIdx(Record *Def) argument
1242 getReg(Record *Def) argument
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H A DInstrDocsEmitter.cpp196 for (Record *Def : II->ImplicitDefs) {
199 OS << "``" << Def->getName() << "``";
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.h107 virtual void computeOperandLatency(SDNode *Def, SDNode *Use,
H A DScheduleDAGSDNodes.cpp111 static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, argument
123 if (Def->getOpcode() == ISD::CopyFromReg &&
124 cast<RegisterSDNode>(Def->getOperand(1))->getReg() == Reg) {
126 } else if (Def->isMachineOpcode()) {
127 const MCInstrDesc &II = TII->get(Def->getMachineOpcode());
135 TRI->getMinimalPhysRegClass(Reg, Def->getSimpleValueType(ResNo));
647 void ScheduleDAGSDNodes::computeOperandLatency(SDNode *Def, SDNode *Use,
660 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCBranchCoalescing.cpp434 for (auto &Def : MI.defs()) { // Looking at Def
435 for (auto &Use : MRI->use_instructions(Def.getReg())) {
545 for (auto &Def : I->defs())
546 for (auto &Use : MRI->use_instructions(Def.getReg())) {
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/MCA/
H A DInstruction.h425 [](const WriteState &Def) { return Def.getNumUsers() > 0; });
430 for (const WriteState &Def : Defs)
431 NumUsers += Def.getNumUsers();
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp173 /// Answer the following question: Can Def be one of the definition
545 const MachineOperand &Def = MI.getOperand(0); local
547 assert(Def.isReg() && Def.isDef() && "Expected reg def");
549 int DefIdx = mapRegToGPRIndex(Def.getReg());
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86LoadValueInjectionLoadHardening.cpp364 [&](NodeAddr<DefNode *> Def) {
365 if (Transmitters.find(Def.Id) != Transmitters.end())
366 return; // Already analyzed `Def`
368 // Use RDF to find all the uses of `Def`
370 RegisterRef DefReg = DFG.getPRI().normalize(Def.Addr->getRegRef(DFG));
371 for (auto UseID : L.getAllReachedUses(DefReg, Def)) {
386 // For each use of `Def`, we want to know whether:
387 // (1) The use can leak the Def'ed value,
388 // (2) The use can further propagate the Def'ed value to more defs
391 continue; // Already visited this use of `Def`
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/freebsd-13-stable/tools/tools/shlib-compat/
H A Dshlib-compat.py245 class Def(object): class in inherits:object
299 if isinstance(v, Def):
317 class AnonymousDef(Def):
319 Def.__init__(self, id, None, **kwargs)
345 class BaseTypeDef(Def):
364 class TypeAliasDef(Def):
374 class EnumerationTypeDef(Def):
407 class FunctionDef(Def):
416 class FunctionTypeDef(Def):
425 class ParameterDef(Def)
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRDFGraph.h78 // - Def node contains: reaching def, sibling, first reached def, and first
86 // |Def |Use | |
88 // | V |Def |Def
164 // - Def.
275 Def = 0x0001 << 2, // 001 member in struct:llvm::rdf::NodeAttrs
287 Preserving = 0x0008 << 5, // 0001000, Def can keep original bits.
491 Def_struct Def; member in union:NodeBase::Ref_struct::__anon3169
549 return getKind() == NodeAttrs::Def;
560 return Ref.Def
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/freebsd-13-stable/contrib/llvm-project/clang/lib/Analysis/
H A DCallGraph.cpp98 if (FunctionDecl *Def = Ctor->getDefinition())
99 addCalledDecl(Def, E);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DSSAUpdaterBulk.cpp141 for (auto &Def : R.Defines)
142 DefBlocks.insert(Def.first);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DRDFDeadCode.cpp211 if (KindA == NodeAttrs::Use && KindB == NodeAttrs::Def)
213 if (KindA == NodeAttrs::Def && KindB == NodeAttrs::Use)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlan.h265 Value *get(VPValue *Def, unsigned Part) {
266 // If Values have been set for this Def return the one relevant for \p Part.
267 if (Data.PerPartOutput.count(Def))
268 return Data.PerPartOutput[Def][Part];
269 // Def is managed by ILV: bring the Values from ValueMap.
270 return Callback.getOrCreateVectorValues(VPValue2Value[Def], Part);
274 Value *get(VPValue *Def, const VPIteration &Instance) {
275 // If the Def is managed directly by VPTransformState, extract the lane from
280 if (Data.PerPartOutput.count(Def)) {
281 auto *VecPart = Data.PerPartOutput[Def][Instanc
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