Searched refs:AM (Results 326 - 350 of 375) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DScalarizer.cpp963 PreservedAnalyses ScalarizerPass::run(Function &F, FunctionAnalysisManager &AM) { argument
967 DominatorTree *DT = &AM.getResult<DominatorTreeAnalysis>(F);
H A DNewGVN.cpp4230 PreservedAnalyses NewGVNPass::run(Function &F, AnalysisManager<Function> &AM) {
4234 auto &AC = AM.getResult<AssumptionAnalysis>(F);
4235 auto &DT = AM.getResult<DominatorTreeAnalysis>(F);
4236 auto &TLI = AM.getResult<TargetLibraryAnalysis>(F);
4237 auto &AA = AM.getResult<AAManager>(F);
4238 auto &MSSA = AM.getResult<MemorySSAAnalysis>(F).getMSSA();
H A DSCCP.cpp1732 PreservedAnalyses SCCPPass::run(Function &F, FunctionAnalysisManager &AM) { argument
1734 auto &TLI = AM.getResult<TargetLibraryAnalysis>(F);
H A DGVNSink.cpp916 PreservedAnalyses GVNSinkPass::run(Function &F, FunctionAnalysisManager &AM) {
H A DLoopPredication.cpp358 PreservedAnalyses LoopPredicationPass::run(Loop &L, LoopAnalysisManager &AM, argument
H A DRewriteStatepointsForGC.cpp129 ModuleAnalysisManager &AM) {
131 auto &FAM = AM.getResult<FunctionAnalysisManagerModuleProxy>(M).getManager();
128 run(Module &M, ModuleAnalysisManager &AM) argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1132 /// by AM is legal for this target, for a load/store of the specified type.
1133 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
1152 /// mode represented by AM for this target, for a load/store
1154 /// If the AM is supported, the return value must be >= 0.
1155 /// If the AM is not supported, it returns a negative value.
1156 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/
H A DAddressSanitizer.cpp1163 ModuleAnalysisManager &AM) {
1173 AnalysisManager<Function> &AM) {
1174 auto &MAMProxy = AM.getResult<ModuleAnalysisManagerFunctionProxy>(F);
1177 const TargetLibraryInfo *TLI = &AM.getResult<TargetLibraryAnalysis>(F);
1198 AnalysisManager<Module> &AM) {
1199 GlobalsMetadata &GlobalsMD = AM.getResult<ASanGlobalsMetadataAnalysis>(M);
1162 run(Module &M, ModuleAnalysisManager &AM) argument
1172 run(Function &F, AnalysisManager<Function> &AM) argument
1197 run(Module &M, AnalysisManager<Module> &AM) argument
H A DGCOVProfiling.cpp569 ModuleAnalysisManager &AM) {
573 AM.getResult<FunctionAnalysisManagerModuleProxy>(M).getManager();
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp5662 PreservedAnalyses SLPVectorizerPass::run(Function &F, FunctionAnalysisManager &AM) {
5663 auto *SE = &AM.getResult<ScalarEvolutionAnalysis>(F);
5664 auto *TTI = &AM.getResult<TargetIRAnalysis>(F);
5665 auto *TLI = AM.getCachedResult<TargetLibraryAnalysis>(F);
5666 auto *AA = &AM.getResult<AAManager>(F);
5667 auto *LI = &AM.getResult<LoopAnalysis>(F);
5668 auto *DT = &AM.getResult<DominatorTreeAnalysis>(F);
5669 auto *AC = &AM.getResult<AssumptionAnalysis>(F);
5670 auto *DB = &AM.getResult<DemandedBitsAnalysis>(F);
5671 auto *ORE = &AM
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp6924 SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
6945 return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, MemVT, MMO);
6948 SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
6969 bool Indexed = AM != ISD::UNINDEXED;
6979 dl.getIROrder(), VTs, AM, ExtType, MemVT, MMO));
6986 auto *N = newSDNode<LoadSDNode>(dl.getIROrder(), dl.getDebugLoc(), VTs, AM,
7035 ISD::MemIndexedMode AM) {
7042 return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(), dl,
7166 ISD::MemIndexedMode AM) {
7180 auto *N = newSDNode<StoreSDNode>(dl.getIROrder(), dl.getDebugLoc(), VTs, AM,
[all...]
H A DDAGCombiner.cpp1010 TargetLoweringBase::AddrMode AM; local
1011 AM.HasBaseReg = true;
1012 AM.BaseOffs = C2APIntVal.getSExtValue();
1016 if (!TLI.isLegalAddressingMode(DAG.getDataLayout(), AM, AccessTy, AS))
1020 AM.BaseOffs = CombinedValue;
1021 if (!TLI.isLegalAddressingMode(DAG.getDataLayout(), AM, AccessTy, AS))
14213 TargetLowering::AddrMode AM;
14215 AM.HasBaseReg = true;
14219 AM.BaseOffs = Offset->getSExtValue();
14222 AM
14307 ISD::MemIndexedMode AM = ISD::UNINDEXED; local
14506 shouldCombineToPostInc(SDNode *N, SDValue Ptr, SDNode *PtrUse, SDValue &BasePtr, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG, const TargetLowering &TLI) argument
14555 getPostIndexedLoadStoreOp(SDNode *N, bool &IsLoad, bool &IsMasked, SDValue &Ptr, SDValue &BasePtr, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG, const TargetLowering &TLI) argument
14604 ISD::MemIndexedMode AM = ISD::UNINDEXED; local
14646 ISD::MemIndexedMode AM = LD->getAddressingMode(); local
[all...]
H A DLegalizeFloatTypes.cpp2428 AtomicSDNode *AM = cast<AtomicSDNode>(N); local
2431 SDValue CastVal = BitConvertToInteger(AM->getVal());
2437 { AM->getChain(), AM->getBasePtr(), CastVal },
2438 AM->getMemOperand());
H A DLegalizeDAG.cpp4789 AtomicSDNode *AM = cast<AtomicSDNode>(Node);
4791 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NVT, AM->getVal());
4794 assert(AM->getMemoryVT().getSizeInBits() == NVT.getSizeInBits() &&
4800 { AM->getChain(), AM->getBasePtr(), CastVal },
4801 AM->getMemOperand());
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp4192 /// by AM is legal for this target, for a load/store of the specified type.
4197 const AddrMode &AM, Type *Ty,
4208 if (AM.BaseGV) {
4209 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale;
4212 switch (AM.Scale) {
4216 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
4196 isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp299 const AddrMode &AM, Type *Ty,
303 if (AM.BaseGV)
307 if (!isInt<12>(AM.BaseOffs))
310 switch (AM.Scale) {
314 if (!AM.HasBaseReg) // allow "r+i".
298 isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const argument
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h2302 /// Return true if the addressing mode represented by AM is legal for this
2312 virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
2317 /// represented by AM for this target, for a load/store of the specified type.
2319 /// If the AM is supported, the return value must be >= 0.
2320 /// If the AM is not supported, it returns a negative value.
2323 virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
2325 // Default: assume that any scaling factor used in a legal AM is free.
2326 if (isLegalAddressingMode(DL, AM, Ty, AS))
3138 ISD::MemIndexedMode &/*AM*/,
3149 ISD::MemIndexedMode &/*AM*/,
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp565 const AddrMode &AM,
571 if (AM.BaseOffs < 0)
575 if (AM.Scale != 0)
564 isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp10220 /// by AM is legal for this target, for a load/store of the specified type.
10222 const AddrMode &AM, Type *Ty,
10232 if (AM.BaseGV)
10236 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
10241 return AM.HasBaseReg && !AM.BaseOffs && !AM.Scale;
10253 if (!AM
10221 isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const argument
10279 getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const argument
14211 getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, bool &IsInc, SelectionDAG &DAG) const argument
14235 getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const argument
14257 getPostIndexedAddressParts( SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const argument
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/IPO/
H A DMergeFunctions.cpp325 ModuleAnalysisManager &AM) {
324 run(Module &M, ModuleAnalysisManager &AM) argument
H A DWholeProgramDevirt.cpp745 ModuleAnalysisManager &AM) {
746 auto &FAM = AM.getResult<FunctionAnalysisManagerModuleProxy>(M).getManager();
744 run(Module &M, ModuleAnalysisManager &AM) argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp451 ISD::MemIndexedMode AM = LD->getAddressingMode(); local
452 if (AM != ISD::UNINDEXED) {
560 ISD::MemIndexedMode AM = ST->getAddressingMode(); local
561 if (AM != ISD::UNINDEXED) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.h666 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp16440 const AddrMode &AM, Type *Ty,
16442 if (isLegalAddressingMode(DL, AM, Ty, AS)) {
16444 return AM.Scale < 0 ? 1 : 0; // positive offsets execute faster
16598 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM, argument
16600 int Scale = AM.Scale;
16622 if (!AM.HasBaseReg && Scale == 2)
16636 bool ARMTargetLowering::isLegalT1ScaledAddressingMode(const AddrMode &AM, argument
16638 const int Scale = AM.Scale;
16648 return (Scale == 1) || (!AM.HasBaseReg && Scale == 2);
16652 /// by AM i
16439 getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const argument
16653 isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const argument
16887 getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const argument
16947 getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const argument
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp1340 ISD::MemIndexedMode &AM,
1362 AM = ISD::POST_INC;
1337 getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const argument

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