/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreISelDAGToDAG.cpp | 95 if (Addr.getOpcode() == ISD::ADD) {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiInstrInfo.cpp | 66 .addImm(LPAC::ADD); 85 .addImm(LPAC::ADD); 765 !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD))
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 689 // Also, try to fold ADD into CSINC/CSINV.. 690 setTargetDAGCombine(ISD::ADD); 1074 setOperationAction(ISD::ADD, VT, Custom); 2447 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul, 3031 if (Opcode == ISD::ADD || Opcode == ISD::SUB) { 3042 if (Opcode == ISD::ADD || Opcode == ISD::SUB) { 3065 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPCR_32, 3585 case ISD::ADD: 3588 llvm_unreachable("Unexpected request to lower ISD::ADD"); 3994 DAG.getNode(ISD::ADD, D [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 716 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT); 734 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT); 743 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT); 764 N = fastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill); 770 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT); 1849 return selectBinaryOp(I, ISD::ADD);
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H A D | LegalizeDAG.cpp | 602 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1611 ISD::ADD : ISD::SUB; 2519 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset); 2815 SDValue Offset = DAG.getNode(ISD::ADD, dl, 2823 Results.push_back(DAG.getNode(ISD::ADD, dl, FA.getValueType(), 3340 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 3346 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT)); 3347 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 3510 unsigned Op = IsAdd ? ISD::ADD : ISD::SUB; 3618 SDValue Addr = DAG.getNode(ISD::ADD, d [all...] |
H A D | SelectionDAGBuilder.h | 692 void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.cpp | 77 setOperationAction(ISD::ADD, MVT::i32, Custom); 78 setOperationAction(ISD::ADD, MVT::i64, Custom); 720 case ISD::ADD: { 801 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) { 852 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) { 1227 ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), 1413 Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/ |
H A D | LanaiAsmParser.cpp | 617 Op->Mem.AluOp = LPAC::ADD; 910 unsigned AluOp = LPAC::ADD; 956 Lanai::R0, std::move(Op), LPAC::ADD));
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/freebsd-13-stable/crypto/openssl/crypto/modes/asm/ |
H A D | ghash-c64xplus.pl | 141 || ADD $x1,$x1,$xib ; SHL $x1,1,$xib
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/freebsd-13-stable/contrib/byacc/test/yacc/ |
H A D | quote_calc.tab.c | 150 #define ADD 258 macro 272 0,0,0,0,0,0,"OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV",
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H A D | quote_calc2.tab.c | 150 #define ADD 258 macro 272 0,0,0,0,0,0,"OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV", 284 "expr : expr \"ADD\" expr",
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 424 setOperationAction(ISD::ADD, VT, Expand); 1727 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq); 1831 SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi); 1885 SDValue Add3 = DAG.getNode(ISD::ADD, DL, VT, Mulhi3, One64); 1894 SDValue Add4 = DAG.getNode(ISD::ADD, DL, VT, Add3, One64); 1991 Z = DAG.getNode(ISD::ADD, DL, VT, Z, 2004 DAG.getNode(ISD::ADD, DL, VT, Q, One), Q); 2011 DAG.getNode(ISD::ADD, DL, VT, Q, One), Q); 2056 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign); 2057 RHS = DAG.getNode(ISD::ADD, D [all...] |
H A D | AMDGPUISelDAGToDAG.cpp | 729 // We are selecting i64 ADD here instead of custom lower it during 948 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) && 978 bool IsAdd = Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE; 1351 if (N0.getOpcode() == ISD::ADD) { 1869 Addr.getOpcode() == ISD::ADD) { 2901 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) && 2917 if (Addr.getOpcode() == ISD::ADD
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
H A D | RISCVMCCodeEmitter.cpp | 147 // Expand PseudoAddTPRel to a simple ADD with the correct relocation. 176 // Emit a normal ADD instruction with the given operands. 177 MCInst TmpInst = MCInstBuilder(RISCV::ADD)
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 95 setOperationAction(ISD::ADD, VecTys[i], Legal); 333 setOperationAction(ISD::ADD, Ty, Legal); 819 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1); 1190 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT)); 1227 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT)); 1583 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), 1589 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), 1992 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), 2001 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), 2308 Address = DAG.getNode(ISD::ADD, D [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 1066 setOperationAction(ISD::ADD, MVT::i16, Custom); 1067 setOperationAction(ISD::ADD, MVT::i32, Custom); 1275 setOperationAction(ISD::ADD, VT, HasInt256 ? Legal : Custom); 1424 setOperationAction(ISD::ADD, VT, Custom); 1572 setOperationAction(ISD::ADD, MVT::v32i16, HasBWI ? Legal : Custom); 1574 setOperationAction(ISD::ADD, MVT::v64i8, HasBWI ? Legal : Custom); 1800 setOperationAction(ISD::ADD, VT, Custom); 1965 setTargetDAGCombine(ISD::ADD); 3256 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getFrameIndex(FI, PtrVT), 3461 SDValue FIN = DAG.getNode(ISD::ADD, D [all...] |
/freebsd-13-stable/sbin/setkey/ |
H A D | parse.y | 99 %token ADD GET DELETE DELETEALL FLUSH DUMP 157 : ADD ipaddropts ipaddr ipaddr protocol_spec spi extension_spec algorithm_spec EOT
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/freebsd-13-stable/contrib/llvm-project/lld/ELF/Arch/ |
H A D | PPC64.cpp | 39 ADD = 266, enumerator in enum:XFormOpcd 586 case ADD:
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 981 setTargetDAGCombine(ISD::ADD); 1499 setTargetDAGCombine(ISD::ADD); 2165 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()), 2395 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 2414 SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff); 2416 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset); 3378 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL)); 3393 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot), 3405 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset); 3499 return DAG.getNode(ISD::ADD, d [all...] |
H A D | ARMISelDAGToDAG.cpp | 401 if (N->getOpcode() != ISD::ADD) 652 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB && 725 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB && 726 // ISD::OR that is equivalent to an ISD::ADD. 731 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) { 1098 if (N.getOpcode() != ISD::ADD) 1110 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) { 1141 if (N.getOpcode() == ISD::ADD) { 1266 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB && 1347 if (N.getOpcode() != ISD::ADD [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelDAGToDAG.cpp | 78 case ISD::ADD: {
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/freebsd-13-stable/crypto/openssl/crypto/sha/asm/ |
H A D | sha512-ia64.pl | 85 $ADD="add"; 99 $ADD="padd4";
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/freebsd-13-stable/sys/dev/an/ |
H A D | if_an.c | 774 #define ADD(s, o) ifmedia_add(&sc->an_ifmedia, \ macro 776 ADD(IFM_AUTO, 0); 777 ADD(IFM_AUTO, IFM_IEEE80211_ADHOC); 785 ADD(mword, 0); 786 ADD(mword, IFM_IEEE80211_ADHOC); 791 #undef ADD macro
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 88 setOperationAction(ISD::ADD, T, Legal); 157 setOperationAction(ISD::ADD, T, Legal); 1490 SDValue T3 = DAG.getNode(ISD::ADD, dl, ResTy, {S2, T2}); 1525 SDValue T4 = DAG.getNode(ISD::ADD, dl, ResTy, {T1, LoVec(T3)}); 1527 SDValue T6 = DAG.getNode(ISD::ADD, dl, ResTy, {HiVec(T0), HiVec(T3)}); 1528 SDValue T7 = DAG.getNode(ISD::ADD, dl, ResTy, {T5, T6});
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 858 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 1284 DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset), 1351 if (Op->getOpcode() != ISD::ADD)
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