Searched refs:phy (Results 201 - 225 of 265) sorted by relevance

1234567891011

/freebsd-12-stable/sys/dev/ixl/
H A Dif_ixl.c774 hw->phy.get_link_info = true;
1292 baudrate = ixl_max_aq_speed_to_value(hw->phy.link_info.link_speed);
1487 switch (hw->phy.link_info.phy_type) {
1603 if (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
1605 if (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
H A Dixl_pf_main.c554 fec_abilities = hw->phy.link_info.req_fec_info;
563 if (hw->phy.link_info.fec_info & I40E_AQ_CONFIG_FEC_RS_ENA)
565 else if (hw->phy.link_info.fec_info & I40E_AQ_CONFIG_FEC_KR_ENA)
572 ixl_link_speed_string(hw->phy.link_info.link_speed),
574 (hw->phy.link_info.an_info & I40E_AQ_AN_COMPLETED) ? "True" : "False",
575 (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX &&
576 hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX) ?
577 ixl_fc_string[3] : (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) ?
578 ixl_fc_string[2] : (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX) ?
2451 ixl_link_speed_string(hw->phy
[all...]
H A Dixl_pf_iflib.c387 ixl_add_ifmedia(vsi->media, hw->phy.phy_types);
410 hw->phy.get_link_info = TRUE;
/freebsd-12-stable/sys/dev/usb/net/
H A Dif_muge.c647 * @phy: the number of phy reading from
658 lan78xx_miibus_readreg(device_t dev, int phy, int reg) argument
675 addr = (phy << 11) | (reg << 6) |
698 * @phy: the number of phy writing to
711 lan78xx_miibus_writereg(device_t dev, int phy, int reg, int val) argument
717 if (sc->sc_phyno != phy)
733 addr = (phy << 11) | (reg << 6) |
747 * lan78xx_miibus_statchg - Called to detect phy statu
[all...]
H A Dif_ure.c340 ure_miibus_readreg(device_t dev, int phy, int reg) argument
366 ure_miibus_writereg(device_t dev, int phy, int reg, int val) argument
372 if (sc->sc_phyno != phy)
1007 "timeout waiting for phy to stabilize\n");
/freebsd-12-stable/sys/arm/nvidia/
H A Dtegra_pcie.c54 #include <dev/extres/phy/phy.h>
269 phy_t phy; /* port phy */ member in struct:tegra_pcib_port
964 rv = phy_get_by_ofw_name(sc->dev, node, "pcie-0", &port->phy);
967 "Cannot get 'pcie-0' phy for port %d\n",
1312 rv = phy_enable(sc->ports[i]->phy);
1315 "Cannot enable phy for port %d\n",
H A Dtegra_xhci.c58 #include <dev/extres/phy/phy.h>
404 device_printf(sc->dev, "Cannot get 'usb2-0' phy\n");
409 device_printf(sc->dev, "Cannot get 'usb2-1' phy\n");
414 device_printf(sc->dev, "Cannot get 'usb2-2' phy\n");
419 device_printf(sc->dev, "Cannot get 'usb3-0' phy\n");
588 device_printf(sc->dev, "Cannot enable USB2_0 phy\n");
593 device_printf(sc->dev, "Cannot enable USB2_1 phy\n");
598 device_printf(sc->dev, "Cannot enable USB2_2 phy\n");
603 device_printf(sc->dev, "Cannot enable USB3_0 phy\
[all...]
/freebsd-12-stable/sys/dev/bwi/
H A Dif_bwi.c361 struct bwi_phy *phy; local
442 phy = &mac->mac_phy;
459 if (phy->phy_mode == IEEE80211_MODE_11B ||
460 phy->phy_mode == IEEE80211_MODE_11G) {
461 if (phy->phy_mode == IEEE80211_MODE_11B) {
476 } else if (phy->phy_mode == IEEE80211_MODE_11A) {
481 panic("unknown phymode %d\n", phy->phy_mode);
1687 struct bwi_phy *phy; local
1695 phy = &mac->mac_phy;
1698 switch (phy
[all...]
/freebsd-12-stable/sys/dev/et/
H A Dif_et.c422 et_miibus_readreg(device_t dev, int phy, int reg) argument
432 val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK;
449 "read phy %d, reg %d timed out\n", phy, reg);
466 et_miibus_writereg(device_t dev, int phy, int reg, int val0) argument
476 val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK;
494 "write phy %d, reg %d timed out\n", phy, reg);
495 et_miibus_readreg(dev, phy, reg);
/freebsd-12-stable/sys/dev/usb/wlan/
H A Dif_run.c510 enum ieee80211_phytype phy; member in struct:rt2860_rate
2957 uint16_t phy; local
2969 phy = le16toh(rxwi->phy);
2970 switch (phy & RT2860_PHY_MODE) {
2972 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) {
2978 if (phy & RT2860_PHY_SHPRE)
2982 switch (phy & RT2860_PHY_MCS) {
3245 if (le16toh(txwi->phy) & RT2860_PHY_SHPRE)
3389 if (rt2860_rates[ridx].phy
[all...]
H A Dif_runreg.h780 uint16_t phy; member in struct:rt2860_txwi
850 uint16_t phy; member in struct:rt2860_rxwi
/freebsd-12-stable/sys/dev/re/
H A Dif_re.c449 re_gmii_readreg(device_t dev, int phy, int reg) argument
487 re_gmii_writereg(device_t dev, int phy, int reg, int data) argument
519 re_miibus_readreg(device_t dev, int phy, int reg) argument
528 rval = re_gmii_readreg(dev, phy, reg);
561 device_printf(sc->rl_dev, "bad phy register\n");
573 re_miibus_writereg(device_t dev, int phy, int reg, int data) argument
582 rval = re_gmii_writereg(dev, phy, reg, data);
611 device_printf(sc->rl_dev, "bad phy register\n");
1221 phy, reg, rid; local
1665 phy
[all...]
/freebsd-12-stable/sys/dev/nge/
H A Dif_nge.c415 nge_miibus_readreg(device_t dev, int phy, int reg) argument
423 if (phy != 0)
455 "bad phy register read : %d\n", reg);
461 return (mii_bitbang_readreg(dev, &nge_mii_bitbang_ops, phy, reg));
465 nge_miibus_writereg(device_t dev, int phy, int reg, int data) argument
472 if (phy != 0)
497 "bad phy register write : %d\n", reg);
504 mii_bitbang_writereg(dev, &nge_mii_bitbang_ops, phy, reg, data);
/freebsd-12-stable/sys/mips/atheros/
H A Dif_arge.c1112 arge_miibus_readreg(device_t dev, int phy, int reg) argument
1116 uint32_t addr = (phy << MAC_MII_PHY_ADDR_SHIFT)
1141 "%s: phy=%d, reg=%02x, value[%08x]=%04x\n",
1142 __func__, phy, reg, addr, result);
1148 arge_miibus_writereg(device_t dev, int phy, int reg, int data) argument
1152 (phy << MAC_MII_PHY_ADDR_SHIFT) | (reg & MAC_MII_REG_MASK);
1154 ARGEDEBUG(sc, ARGE_DBG_MII, "%s: phy=%d, reg=%02x, value=%04x\n", __func__,
1155 phy, reg, data);
/freebsd-12-stable/sys/dev/ice/
H A Dif_ice_iflib.c1742 struct ice_link_status *li = &sc->hw.port_info->phy.link_info;
1942 pi->phy.get_link_info = true;
1945 if (pi->phy.link_info.link_info & ICE_AQ_MEDIA_AVAILABLE) {
2438 sc->hw.port_info->phy.get_link_info = true;
/freebsd-12-stable/sys/dev/vte/
H A Dif_vte.c173 vte_miibus_readreg(device_t dev, int phy, int reg) argument
181 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT));
189 device_printf(sc->vte_dev, "phy read timeout : %d\n", reg);
197 vte_miibus_writereg(device_t dev, int phy, int reg, int val) argument
206 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT));
214 device_printf(sc->vte_dev, "phy write timeout : %d\n", reg);
/freebsd-12-stable/sys/dev/tsec/
H A Dif_tsec.c1576 tsec_miibus_readreg(device_t dev, int phy, int reg) argument
1585 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1600 tsec_miibus_writereg(device_t dev, int phy, int reg, int value) argument
1608 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
/freebsd-12-stable/sys/dev/sge/
H A Dif_sge.c333 sge_miibus_readreg(device_t dev, int phy, int reg) argument
340 CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) |
357 sge_miibus_writereg(device_t dev, int phy, int reg, int data) argument
364 CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) |
/freebsd-12-stable/sys/dev/axgbe/
H A Dxgbe.h179 #define XGBE_PHY_MODE_PROPERTY "phy-mode"
818 struct xgbe_phy phy; member in struct:xgbe_prv_data
/freebsd-12-stable/sys/mips/atheros/ar531x/
H A Dif_are.c454 are_miibus_readreg(device_t dev, int phy, int reg) argument
460 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT);
471 are_miibus_writereg(device_t dev, int phy, int reg, int data) argument
481 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT) |
/freebsd-12-stable/sys/arm/ralink/
H A Dif_fv.c522 fv_miibus_readreg(device_t dev, int phy, int reg) argument
530 fv_miibus_writebits(sc, phy, 5);
541 fv_miibus_writereg(device_t dev, int phy, int reg, int data) argument
548 fv_miibus_writebits(sc, phy, 5);
/freebsd-12-stable/sys/dev/cadence/
H A Dif_cgem.c908 /* Poll the phy. */
1318 cgem_miibus_readreg(device_t dev, int phy, int reg) argument
1326 (phy << CGEM_PHY_MAINT_PHY_ADDR_SHIFT) |
1334 device_printf(dev, "phy read timeout: %d\n", reg);
1352 cgem_miibus_writereg(device_t dev, int phy, int reg, int data) argument
1360 (phy << CGEM_PHY_MAINT_PHY_ADDR_SHIFT) |
1369 device_printf(dev, "phy write timeout: %d\n", reg);
1721 /* Attach phy to mii bus. */
/freebsd-12-stable/sys/dev/hptiop/
H A Dhptiop.c2678 u_int64_t phy; local
2681 phy = ((u_int64_t)segs->ds_addr + 0x1F)
2686 hba->ctlcfgcmd_phy = phy;
2690 phy += 0x800;
2693 hba->u.mvfrey.inlist_phy = phy;
2696 phy += list_count * sizeof(struct mvfrey_inlist_entry);
2699 hba->u.mvfrey.outlist_phy = phy;
2702 phy += list_count * sizeof(struct mvfrey_outlist_entry);
2705 hba->u.mvfrey.outlist_cptr_phy = phy;
/freebsd-12-stable/sys/dev/sf/
H A Dif_sfreg.h579 #define SF_PHY_REG(phy, reg) \
580 (SF_MIIADDR_BASE + ((phy) * SF_MII_BLOCKS * sizeof(uint32_t)) + \
/freebsd-12-stable/sys/dev/rt/
H A Dif_rt.c2755 rt_miibus_readreg(device_t dev, int phy, int reg) argument
2765 if (phy == 31) {
2780 dat = ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) |
2790 rt_miibus_writereg(device_t dev, int phy, int reg, int val) argument
2798 ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) |

Completed in 307 milliseconds

1234567891011