1/* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 * 116 * $FreeBSD$ 117 */ 118 119#ifndef __XGBE_H__ 120#define __XGBE_H__ 121 122#include "xgbe_osdep.h" 123 124/* From linux/dcbnl.h */ 125#define IEEE_8021QAZ_MAX_TCS 8 126 127#define XGBE_DRV_NAME "amd-xgbe" 128#define XGBE_DRV_VERSION "1.0.2" 129#define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver" 130 131/* Descriptor related defines */ 132#define XGBE_TX_DESC_CNT 512 133#define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3) 134#define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1) 135#define XGBE_RX_DESC_CNT 512 136 137#define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 138 139/* Descriptors required for maximum contiguous TSO/GSO packet */ 140#define XGBE_TX_MAX_SPLIT ((GSO_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1) 141 142/* Maximum possible descriptors needed for an SKB: 143 * - Maximum number of SKB frags 144 * - Maximum descriptors for contiguous TSO/GSO packet 145 * - Possible context descriptor 146 * - Possible TSO header descriptor 147 */ 148#define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2) 149 150#define XGBE_RX_MIN_BUF_SIZE 1522 151#define XGBE_RX_BUF_ALIGN 64 152#define XGBE_SKB_ALLOC_SIZE 256 153#define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */ 154 155#define XGBE_MAX_DMA_CHANNELS 16 156#define XGBE_MAX_QUEUES 16 157#define XGBE_DMA_STOP_TIMEOUT 5 158 159/* DMA cache settings - Outer sharable, write-back, write-allocate */ 160#define XGBE_DMA_OS_AXDOMAIN 0x2 161#define XGBE_DMA_OS_ARCACHE 0xb 162#define XGBE_DMA_OS_AWCACHE 0xf 163 164/* DMA cache settings - System, no caches used */ 165#define XGBE_DMA_SYS_AXDOMAIN 0x3 166#define XGBE_DMA_SYS_ARCACHE 0x0 167#define XGBE_DMA_SYS_AWCACHE 0x0 168 169#define XGBE_DMA_INTERRUPT_MASK 0x31c7 170 171#define XGMAC_MIN_PACKET 60 172#define XGMAC_STD_PACKET_MTU 1500 173#define XGMAC_MAX_STD_PACKET 1518 174#define XGMAC_JUMBO_PACKET_MTU 9000 175#define XGMAC_MAX_JUMBO_PACKET 9018 176 177/* Common property names */ 178#define XGBE_MAC_ADDR_PROPERTY "mac-address" 179#define XGBE_PHY_MODE_PROPERTY "phy-mode" 180#define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt" 181#define XGBE_SPEEDSET_PROPERTY "amd,speed-set" 182#define XGBE_BLWC_PROPERTY "amd,serdes-blwc" 183#define XGBE_CDR_RATE_PROPERTY "amd,serdes-cdr-rate" 184#define XGBE_PQ_SKEW_PROPERTY "amd,serdes-pq-skew" 185#define XGBE_TX_AMP_PROPERTY "amd,serdes-tx-amp" 186#define XGBE_DFE_CFG_PROPERTY "amd,serdes-dfe-tap-config" 187#define XGBE_DFE_ENA_PROPERTY "amd,serdes-dfe-tap-enable" 188 189/* Device-tree clock names */ 190#define XGBE_DMA_CLOCK "dma_clk" 191#define XGBE_PTP_CLOCK "ptp_clk" 192 193/* ACPI property names */ 194#define XGBE_ACPI_DMA_FREQ "amd,dma-freq" 195#define XGBE_ACPI_PTP_FREQ "amd,ptp-freq" 196 197/* Timestamp support - values based on 50MHz PTP clock 198 * 50MHz => 20 nsec 199 */ 200#define XGBE_TSTAMP_SSINC 20 201#define XGBE_TSTAMP_SNSINC 0 202 203/* Driver PMT macros */ 204#define XGMAC_DRIVER_CONTEXT 1 205#define XGMAC_IOCTL_CONTEXT 2 206 207#define XGBE_FIFO_MAX 81920 208 209#define XGBE_TC_MIN_QUANTUM 10 210 211/* Helper macro for descriptor handling 212 * Always use XGBE_GET_DESC_DATA to access the descriptor data 213 * since the index is free-running and needs to be and-ed 214 * with the descriptor count value of the ring to index to 215 * the proper descriptor data. 216 */ 217#define XGBE_GET_DESC_DATA(_ring, _idx) \ 218 ((_ring)->rdata + \ 219 ((_idx) & ((_ring)->rdesc_count - 1))) 220 221/* Default coalescing parameters */ 222#define XGMAC_INIT_DMA_TX_USECS 1000 223#define XGMAC_INIT_DMA_TX_FRAMES 25 224 225#define XGMAC_MAX_DMA_RIWT 0xff 226#define XGMAC_INIT_DMA_RX_USECS 30 227#define XGMAC_INIT_DMA_RX_FRAMES 25 228 229/* Flow control queue count */ 230#define XGMAC_MAX_FLOW_CONTROL_QUEUES 8 231 232/* Maximum MAC address hash table size (256 bits = 8 bytes) */ 233#define XGBE_MAC_HASH_TABLE_SIZE 8 234 235/* Receive Side Scaling */ 236#define XGBE_RSS_HASH_KEY_SIZE 40 237#define XGBE_RSS_MAX_TABLE_SIZE 256 238#define XGBE_RSS_LOOKUP_TABLE_TYPE 0 239#define XGBE_RSS_HASH_KEY_TYPE 1 240 241/* Auto-negotiation */ 242#define XGBE_AN_MS_TIMEOUT 500 243#define XGBE_LINK_TIMEOUT 10 244 245#define XGBE_AN_INT_CMPLT 0x01 246#define XGBE_AN_INC_LINK 0x02 247#define XGBE_AN_PG_RCV 0x04 248#define XGBE_AN_INT_MASK 0x07 249 250/* Rate-change complete wait/retry count */ 251#define XGBE_RATECHANGE_COUNT 500 252 253/* Default SerDes settings */ 254#define XGBE_SPEED_10000_BLWC 0 255#define XGBE_SPEED_10000_CDR 0x7 256#define XGBE_SPEED_10000_PLL 0x1 257#define XGBE_SPEED_10000_PQ 0x12 258#define XGBE_SPEED_10000_RATE 0x0 259#define XGBE_SPEED_10000_TXAMP 0xa 260#define XGBE_SPEED_10000_WORD 0x7 261#define XGBE_SPEED_10000_DFE_TAP_CONFIG 0x1 262#define XGBE_SPEED_10000_DFE_TAP_ENABLE 0x7f 263 264#define XGBE_SPEED_2500_BLWC 1 265#define XGBE_SPEED_2500_CDR 0x2 266#define XGBE_SPEED_2500_PLL 0x0 267#define XGBE_SPEED_2500_PQ 0xa 268#define XGBE_SPEED_2500_RATE 0x1 269#define XGBE_SPEED_2500_TXAMP 0xf 270#define XGBE_SPEED_2500_WORD 0x1 271#define XGBE_SPEED_2500_DFE_TAP_CONFIG 0x3 272#define XGBE_SPEED_2500_DFE_TAP_ENABLE 0x0 273 274#define XGBE_SPEED_1000_BLWC 1 275#define XGBE_SPEED_1000_CDR 0x2 276#define XGBE_SPEED_1000_PLL 0x0 277#define XGBE_SPEED_1000_PQ 0xa 278#define XGBE_SPEED_1000_RATE 0x3 279#define XGBE_SPEED_1000_TXAMP 0xf 280#define XGBE_SPEED_1000_WORD 0x1 281#define XGBE_SPEED_1000_DFE_TAP_CONFIG 0x3 282#define XGBE_SPEED_1000_DFE_TAP_ENABLE 0x0 283 284struct xgbe_prv_data; 285 286struct xgbe_packet_data { 287 struct mbuf *m; 288 289 unsigned int attributes; 290 291 unsigned int errors; 292 293 unsigned int rdesc_count; 294 unsigned int length; 295 296 u64 rx_tstamp; 297 298 unsigned int tx_packets; 299 unsigned int tx_bytes; 300}; 301 302/* Common Rx and Tx descriptor mapping */ 303struct xgbe_ring_desc { 304 __le32 desc0; 305 __le32 desc1; 306 __le32 desc2; 307 __le32 desc3; 308}; 309 310/* Tx-related ring data */ 311struct xgbe_tx_ring_data { 312 unsigned int packets; /* BQL packet count */ 313 unsigned int bytes; /* BQL byte count */ 314}; 315 316/* Rx-related ring data */ 317struct xgbe_rx_ring_data { 318 unsigned short hdr_len; /* Length of received header */ 319 unsigned short len; /* Length of received packet */ 320}; 321 322/* Structure used to hold information related to the descriptor 323 * and the packet associated with the descriptor (always use 324 * use the XGBE_GET_DESC_DATA macro to access this data from the ring) 325 */ 326struct xgbe_ring_data { 327 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */ 328 bus_addr_t rdata_paddr; 329 330 bus_dma_tag_t mbuf_dmat; 331 bus_dmamap_t mbuf_map; 332 bus_addr_t mbuf_hdr_paddr; 333 bus_addr_t mbuf_data_paddr; 334 bus_size_t mbuf_len; 335 336 int mbuf_free; 337 struct mbuf *mb; 338 339 struct xgbe_tx_ring_data tx; /* Tx-related data */ 340 struct xgbe_rx_ring_data rx; /* Rx-related data */ 341}; 342 343struct xgbe_ring { 344 /* Ring lock - used just for TX rings at the moment */ 345 spinlock_t lock; 346 347 /* Per packet related information */ 348 struct xgbe_packet_data packet_data; 349 350 /* Virtual/DMA addresses and count of allocated descriptor memory */ 351 struct xgbe_ring_desc *rdesc; 352 bus_dmamap_t rdesc_map; 353 bus_dma_tag_t rdesc_dmat; 354 bus_addr_t rdesc_paddr; 355 unsigned int rdesc_count; 356 357 bus_dma_tag_t mbuf_dmat; 358 bus_dmamap_t mbuf_map; 359 360 /* Array of descriptor data corresponding the descriptor memory 361 * (always use the XGBE_GET_DESC_DATA macro to access this data) 362 */ 363 struct xgbe_ring_data *rdata; 364 365 /* Ring index values 366 * cur - Tx: index of descriptor to be used for current transfer 367 * Rx: index of descriptor to check for packet availability 368 * dirty - Tx: index of descriptor to check for transfer complete 369 * Rx: index of descriptor to check for buffer reallocation 370 */ 371 unsigned int cur; 372 unsigned int dirty; 373 374 /* Coalesce frame count used for interrupt bit setting */ 375 unsigned int coalesce_count; 376 377 union { 378 struct { 379 unsigned int queue_stopped; 380 unsigned int xmit_more; 381 unsigned short cur_mss; 382 unsigned short cur_vlan_ctag; 383 } tx; 384 }; 385} __aligned(CACHE_LINE_SIZE); 386 387/* Structure used to describe the descriptor rings associated with 388 * a DMA channel. 389 */ 390struct xgbe_channel { 391 char name[16]; 392 393 /* Address of private data area for device */ 394 struct xgbe_prv_data *pdata; 395 396 /* Queue index and base address of queue's DMA registers */ 397 unsigned int queue_index; 398 bus_space_tag_t dma_tag; 399 bus_space_handle_t dma_handle; 400 401 /* Per channel interrupt irq number */ 402 struct resource *dma_irq_res; 403 void *dma_irq_tag; 404 405 unsigned int saved_ier; 406 407 struct xgbe_ring *tx_ring; 408 struct xgbe_ring *rx_ring; 409} __aligned(CACHE_LINE_SIZE); 410 411enum xgbe_state { 412 XGBE_DOWN, 413 XGBE_LINK_INIT, 414 XGBE_LINK_ERR, 415}; 416 417enum xgbe_int { 418 XGMAC_INT_DMA_CH_SR_TI, 419 XGMAC_INT_DMA_CH_SR_TPS, 420 XGMAC_INT_DMA_CH_SR_TBU, 421 XGMAC_INT_DMA_CH_SR_RI, 422 XGMAC_INT_DMA_CH_SR_RBU, 423 XGMAC_INT_DMA_CH_SR_RPS, 424 XGMAC_INT_DMA_CH_SR_TI_RI, 425 XGMAC_INT_DMA_CH_SR_FBE, 426 XGMAC_INT_DMA_ALL, 427}; 428 429enum xgbe_int_state { 430 XGMAC_INT_STATE_SAVE, 431 XGMAC_INT_STATE_RESTORE, 432}; 433 434enum xgbe_speed { 435 XGBE_SPEED_1000 = 0, 436 XGBE_SPEED_2500, 437 XGBE_SPEED_10000, 438 XGBE_SPEEDS, 439}; 440 441enum xgbe_an { 442 XGBE_AN_READY = 0, 443 XGBE_AN_PAGE_RECEIVED, 444 XGBE_AN_INCOMPAT_LINK, 445 XGBE_AN_COMPLETE, 446 XGBE_AN_NO_LINK, 447 XGBE_AN_ERROR, 448}; 449 450enum xgbe_rx { 451 XGBE_RX_BPA = 0, 452 XGBE_RX_XNP, 453 XGBE_RX_COMPLETE, 454 XGBE_RX_ERROR, 455}; 456 457enum xgbe_mode { 458 XGBE_MODE_KR = 0, 459 XGBE_MODE_KX, 460}; 461 462enum xgbe_speedset { 463 XGBE_SPEEDSET_1000_10000 = 0, 464 XGBE_SPEEDSET_2500_10000, 465}; 466 467struct xgbe_phy { 468 u32 supported; 469 u32 advertising; 470 u32 lp_advertising; 471 472 int address; 473 474 int autoneg; 475 int speed; 476 int duplex; 477 478 int link; 479 480 int pause_autoneg; 481 int tx_pause; 482 int rx_pause; 483}; 484 485struct xgbe_mmc_stats { 486 /* Tx Stats */ 487 u64 txoctetcount_gb; 488 u64 txframecount_gb; 489 u64 txbroadcastframes_g; 490 u64 txmulticastframes_g; 491 u64 tx64octets_gb; 492 u64 tx65to127octets_gb; 493 u64 tx128to255octets_gb; 494 u64 tx256to511octets_gb; 495 u64 tx512to1023octets_gb; 496 u64 tx1024tomaxoctets_gb; 497 u64 txunicastframes_gb; 498 u64 txmulticastframes_gb; 499 u64 txbroadcastframes_gb; 500 u64 txunderflowerror; 501 u64 txoctetcount_g; 502 u64 txframecount_g; 503 u64 txpauseframes; 504 u64 txvlanframes_g; 505 506 /* Rx Stats */ 507 u64 rxframecount_gb; 508 u64 rxoctetcount_gb; 509 u64 rxoctetcount_g; 510 u64 rxbroadcastframes_g; 511 u64 rxmulticastframes_g; 512 u64 rxcrcerror; 513 u64 rxrunterror; 514 u64 rxjabbererror; 515 u64 rxundersize_g; 516 u64 rxoversize_g; 517 u64 rx64octets_gb; 518 u64 rx65to127octets_gb; 519 u64 rx128to255octets_gb; 520 u64 rx256to511octets_gb; 521 u64 rx512to1023octets_gb; 522 u64 rx1024tomaxoctets_gb; 523 u64 rxunicastframes_g; 524 u64 rxlengtherror; 525 u64 rxoutofrangetype; 526 u64 rxpauseframes; 527 u64 rxfifooverflow; 528 u64 rxvlanframes_gb; 529 u64 rxwatchdogerror; 530}; 531 532struct xgbe_ext_stats { 533 u64 tx_tso_packets; 534 u64 rx_split_header_packets; 535 u64 rx_buffer_unavailable; 536}; 537 538struct xgbe_hw_if { 539 int (*tx_complete)(struct xgbe_ring_desc *); 540 541 int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr); 542 int (*config_rx_mode)(struct xgbe_prv_data *); 543 544 int (*enable_rx_csum)(struct xgbe_prv_data *); 545 int (*disable_rx_csum)(struct xgbe_prv_data *); 546 547 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *); 548 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *); 549 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *); 550 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *); 551 int (*update_vlan_hash_table)(struct xgbe_prv_data *); 552 553 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int); 554 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int); 555 int (*set_gmii_speed)(struct xgbe_prv_data *); 556 int (*set_gmii_2500_speed)(struct xgbe_prv_data *); 557 int (*set_xgmii_speed)(struct xgbe_prv_data *); 558 559 void (*enable_tx)(struct xgbe_prv_data *); 560 void (*disable_tx)(struct xgbe_prv_data *); 561 void (*enable_rx)(struct xgbe_prv_data *); 562 void (*disable_rx)(struct xgbe_prv_data *); 563 564 void (*powerup_tx)(struct xgbe_prv_data *); 565 void (*powerdown_tx)(struct xgbe_prv_data *); 566 void (*powerup_rx)(struct xgbe_prv_data *); 567 void (*powerdown_rx)(struct xgbe_prv_data *); 568 569 int (*init)(struct xgbe_prv_data *); 570 int (*exit)(struct xgbe_prv_data *); 571 572 int (*enable_int)(struct xgbe_channel *, enum xgbe_int); 573 int (*disable_int)(struct xgbe_channel *, enum xgbe_int); 574 void (*dev_xmit)(struct xgbe_channel *); 575 int (*dev_read)(struct xgbe_channel *); 576 void (*tx_desc_init)(struct xgbe_channel *); 577 void (*rx_desc_init)(struct xgbe_channel *); 578 void (*tx_desc_reset)(struct xgbe_ring_data *); 579 void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *, 580 unsigned int); 581 int (*is_last_desc)(struct xgbe_ring_desc *); 582 int (*is_context_desc)(struct xgbe_ring_desc *); 583 void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *); 584 585 /* For FLOW ctrl */ 586 int (*config_tx_flow_control)(struct xgbe_prv_data *); 587 int (*config_rx_flow_control)(struct xgbe_prv_data *); 588 589 /* For RX coalescing */ 590 int (*config_rx_coalesce)(struct xgbe_prv_data *); 591 int (*config_tx_coalesce)(struct xgbe_prv_data *); 592 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int); 593 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int); 594 595 /* For RX and TX threshold config */ 596 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int); 597 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int); 598 599 /* For RX and TX Store and Forward Mode config */ 600 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int); 601 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int); 602 603 /* For TX DMA Operate on Second Frame config */ 604 int (*config_osp_mode)(struct xgbe_prv_data *); 605 606 /* For RX and TX PBL config */ 607 int (*config_rx_pbl_val)(struct xgbe_prv_data *); 608 int (*get_rx_pbl_val)(struct xgbe_prv_data *); 609 int (*config_tx_pbl_val)(struct xgbe_prv_data *); 610 int (*get_tx_pbl_val)(struct xgbe_prv_data *); 611 int (*config_pblx8)(struct xgbe_prv_data *); 612 613 /* For MMC statistics */ 614 void (*rx_mmc_int)(struct xgbe_prv_data *); 615 void (*tx_mmc_int)(struct xgbe_prv_data *); 616 void (*read_mmc_stats)(struct xgbe_prv_data *); 617 618 /* For Receive Side Scaling */ 619 int (*disable_rss)(struct xgbe_prv_data *); 620}; 621 622struct xgbe_phy_if { 623 /* For initial PHY setup */ 624 void (*phy_init)(struct xgbe_prv_data *); 625 626 /* For PHY support when setting device up/down */ 627 int (*phy_reset)(struct xgbe_prv_data *); 628 int (*phy_start)(struct xgbe_prv_data *); 629 void (*phy_stop)(struct xgbe_prv_data *); 630 631 /* For PHY support while device is up */ 632 void (*phy_status)(struct xgbe_prv_data *); 633 int (*phy_config_aneg)(struct xgbe_prv_data *); 634}; 635 636struct xgbe_desc_if { 637 int (*alloc_ring_resources)(struct xgbe_prv_data *); 638 void (*free_ring_resources)(struct xgbe_prv_data *); 639 int (*map_tx_skb)(struct xgbe_channel *, struct mbuf *); 640 int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *, 641 struct xgbe_ring_data *); 642 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *); 643 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *); 644 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *); 645}; 646 647/* This structure contains flags that indicate what hardware features 648 * or configurations are present in the device. 649 */ 650struct xgbe_hw_features { 651 /* HW Version */ 652 unsigned int version; 653 654 /* HW Feature Register0 */ 655 unsigned int gmii; /* 1000 Mbps support */ 656 unsigned int vlhash; /* VLAN Hash Filter */ 657 unsigned int sma; /* SMA(MDIO) Interface */ 658 unsigned int rwk; /* PMT remote wake-up packet */ 659 unsigned int mgk; /* PMT magic packet */ 660 unsigned int mmc; /* RMON module */ 661 unsigned int aoe; /* ARP Offload */ 662 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */ 663 unsigned int eee; /* Energy Efficient Ethernet */ 664 unsigned int tx_coe; /* Tx Checksum Offload */ 665 unsigned int rx_coe; /* Rx Checksum Offload */ 666 unsigned int addn_mac; /* Additional MAC Addresses */ 667 unsigned int ts_src; /* Timestamp Source */ 668 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ 669 670 /* HW Feature Register1 */ 671 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ 672 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ 673 unsigned int adv_ts_hi; /* Advance Timestamping High Word */ 674 unsigned int dma_width; /* DMA width */ 675 unsigned int dcb; /* DCB Feature */ 676 unsigned int sph; /* Split Header Feature */ 677 unsigned int tso; /* TCP Segmentation Offload */ 678 unsigned int dma_debug; /* DMA Debug Registers */ 679 unsigned int rss; /* Receive Side Scaling */ 680 unsigned int tc_cnt; /* Number of Traffic Classes */ 681 unsigned int hash_table_size; /* Hash Table Size */ 682 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ 683 684 /* HW Feature Register2 */ 685 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ 686 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ 687 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ 688 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ 689 unsigned int pps_out_num; /* Number of PPS outputs */ 690 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ 691}; 692 693struct xgbe_prv_data { 694 struct ifnet *netdev; 695 struct platform_device *pdev; 696 struct acpi_device *adev; 697 device_t dev; 698 699 /* ACPI or DT flag */ 700 unsigned int use_acpi; 701 702 /* XGMAC/XPCS related mmio registers */ 703 struct resource *xgmac_res; /* XGMAC CSRs */ 704 struct resource *xpcs_res; /* XPCS MMD registers */ 705 struct resource *rxtx_res; /* SerDes Rx/Tx CSRs */ 706 struct resource *sir0_res; /* SerDes integration registers (1/2) */ 707 struct resource *sir1_res; /* SerDes integration registers (2/2) */ 708 709 /* DMA tag */ 710 bus_dma_tag_t dmat; 711 712 /* XPCS indirect addressing lock */ 713 spinlock_t xpcs_lock; 714 715 /* Flags representing xgbe_state */ 716 unsigned long dev_state; 717 718 struct resource *dev_irq_res; 719 struct resource *chan_irq_res[4]; 720 void *dev_irq_tag; 721 unsigned int per_channel_irq; 722 723 struct xgbe_hw_if hw_if; 724 struct xgbe_phy_if phy_if; 725 struct xgbe_desc_if desc_if; 726 727 /* AXI DMA settings */ 728 unsigned int coherent; 729 unsigned int axdomain; 730 unsigned int arcache; 731 unsigned int awcache; 732 733 /* Service routine support */ 734 struct taskqueue *dev_workqueue; 735 struct task service_work; 736 struct callout service_timer; 737 738 /* Rings for Tx/Rx on a DMA channel */ 739 struct xgbe_channel *channel; 740 unsigned int channel_count; 741 unsigned int tx_ring_count; 742 unsigned int tx_desc_count; 743 unsigned int rx_ring_count; 744 unsigned int rx_desc_count; 745 746 unsigned int tx_q_count; 747 unsigned int rx_q_count; 748 749 /* Tx/Rx common settings */ 750 unsigned int pblx8; 751 752 /* Tx settings */ 753 unsigned int tx_sf_mode; 754 unsigned int tx_threshold; 755 unsigned int tx_pbl; 756 unsigned int tx_osp_mode; 757 758 /* Rx settings */ 759 unsigned int rx_sf_mode; 760 unsigned int rx_threshold; 761 unsigned int rx_pbl; 762 763 /* Tx coalescing settings */ 764 unsigned int tx_usecs; 765 unsigned int tx_frames; 766 767 /* Rx coalescing settings */ 768 unsigned int rx_riwt; 769 unsigned int rx_usecs; 770 unsigned int rx_frames; 771 772 /* Current Rx buffer size */ 773 unsigned int rx_buf_size; 774 775 /* Flow control settings */ 776 unsigned int pause_autoneg; 777 unsigned int tx_pause; 778 unsigned int rx_pause; 779 780 /* Receive Side Scaling settings */ 781 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE]; 782 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE]; 783 u32 rss_options; 784 785 /* Netdev related settings */ 786 unsigned char mac_addr[ETH_ALEN]; 787 struct xgbe_mmc_stats mmc_stats; 788 struct xgbe_ext_stats ext_stats; 789 790 /* Device clocks */ 791 struct clk *sysclk; 792 unsigned long sysclk_rate; 793 struct clk *ptpclk; 794 unsigned long ptpclk_rate; 795 796 /* DCB support */ 797 unsigned int q2tc_map[XGBE_MAX_QUEUES]; 798 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS]; 799 u8 num_tcs; 800 801 /* Hardware features of the device */ 802 struct xgbe_hw_features hw_feat; 803 804 /* Device restart work structure */ 805 struct task restart_work; 806 807 /* Keeps track of power mode */ 808 unsigned int power_down; 809 810 /* Network interface message level setting */ 811 u32 msg_enable; 812 813 /* Current PHY settings */ 814 int phy_link; 815 int phy_speed; 816 817 /* MDIO/PHY related settings */ 818 struct xgbe_phy phy; 819 int mdio_mmd; 820 unsigned long link_check; 821 822 char an_name[IFNAMSIZ + 32]; 823 824 struct resource *an_irq_res; 825 void *an_irq_tag; 826 827 unsigned int speed_set; 828 829 /* SerDes UEFI configurable settings. 830 * Switching between modes/speeds requires new values for some 831 * SerDes settings. The values can be supplied as device 832 * properties in array format. The first array entry is for 833 * 1GbE, second for 2.5GbE and third for 10GbE 834 */ 835 u32 serdes_blwc[XGBE_SPEEDS]; 836 u32 serdes_cdr_rate[XGBE_SPEEDS]; 837 u32 serdes_pq_skew[XGBE_SPEEDS]; 838 u32 serdes_tx_amp[XGBE_SPEEDS]; 839 u32 serdes_dfe_tap_cfg[XGBE_SPEEDS]; 840 u32 serdes_dfe_tap_ena[XGBE_SPEEDS]; 841 842 /* Auto-negotiation state machine support */ 843 unsigned int an_int; 844 struct sx an_mutex; 845 enum xgbe_an an_result; 846 enum xgbe_an an_state; 847 enum xgbe_rx kr_state; 848 enum xgbe_rx kx_state; 849 unsigned int an_supported; 850 unsigned int parallel_detect; 851 unsigned int fec_ability; 852 unsigned long an_start; 853 854 unsigned int lpm_ctrl; /* CTRL1 for resume */ 855}; 856 857/* Function prototypes*/ 858 859int xgbe_open(struct ifnet *); 860int xgbe_close(struct ifnet *); 861int xgbe_xmit(struct ifnet *, struct mbuf *); 862int xgbe_change_mtu(struct ifnet *, int); 863void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *); 864void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *); 865void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *); 866void xgbe_get_all_hw_features(struct xgbe_prv_data *); 867void xgbe_init_rx_coalesce(struct xgbe_prv_data *); 868void xgbe_init_tx_coalesce(struct xgbe_prv_data *); 869 870/* NOTE: Uncomment for function trace log messages in KERNEL LOG */ 871#if 0 872#define YDEBUG 873#define YDEBUG_MDIO 874#endif 875 876/* For debug prints */ 877#ifdef YDEBUG 878#define DBGPR(x...) printf(x) 879#else 880#define DBGPR(x...) do { } while (0) 881#endif 882 883#ifdef YDEBUG_MDIO 884#define DBGPR_MDIO(x...) printf(x) 885#else 886#define DBGPR_MDIO(x...) do { } while (0) 887#endif 888 889#endif 890