/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsISelDAGToDAG.cpp | 50 Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget()); 214 assert((Subtarget->systemSupportsUnalignedAccess() ||
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H A D | MipsCCState.h | 28 const MipsSubtarget &Subtarget);
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H A D | Mips16ISelLowering.cpp | 130 if (!Subtarget.useSoftFloat()) 434 if (Subtarget.inMips16HardFloat()) { 526 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 587 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 651 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 715 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 731 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 765 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 783 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
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H A D | MipsInstrInfo.h | 36 const MipsSubtarget &Subtarget; member in class:llvm::MipsInstrInfo
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H A D | MipsLongBranch.cpp | 259 const MipsSubtarget &Subtarget = local 262 static_cast<const MipsInstrInfo *>(Subtarget.getInstrInfo()); 276 unsigned BalOp = Subtarget.hasMips32r6() ? Mips::BAL : Mips::BAL_BR; 332 if (!Subtarget.isTargetNaCl()) {
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/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.h | 25 const PPCSubtarget &Subtarget; member in class:llvm::PPCFrameLowering
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H A D | PPCTargetMachine.h | 32 PPCSubtarget Subtarget; member in class:llvm::PPCTargetMachine
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H A D | PPCISelLowering.h | 421 const PPCSubtarget &Subtarget; member in class:llvm::PPCTargetLowering 731 const PPCSubtarget &Subtarget) const; 733 const PPCSubtarget &Subtarget) const; 735 const PPCSubtarget &Subtarget) const; 737 const PPCSubtarget &Subtarget) const; 739 const PPCSubtarget &Subtarget) const; 741 const PPCSubtarget &Subtarget) const;
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/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.h | 32 const ARMSubtarget &Subtarget; member in class:llvm::ARMBaseInstrInfo 114 const ARMSubtarget &getSubtarget() const { return Subtarget; } 172 const ARMSubtarget &Subtarget) const; 175 const ARMSubtarget &Subtarget) const; 491 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
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H A D | ARMTargetMachine.cpp | 185 Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) { 190 Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft; 195 if (Subtarget.isTargetGNUAEABI()) 255 if (!Subtarget.hasARMOps()) 256 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
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H A D | ARMAsmPrinter.h | 34 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 36 const ARMSubtarget *Subtarget; member in class:llvm::ARMAsmPrinter
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/freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 199 if (Subtarget->is64Bit()) 374 if (Subtarget->is64Bit()) 682 Subtarget->getStackPointerBias()); 707 if (Subtarget->is64Bit()) 975 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo(); 1189 unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128; 1242 Subtarget->getStackPointerBias() + 1286 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo(); 1426 : TargetLowering(TM), Subtarget(&STI) { 1442 if (Subtarget 2507 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument 2538 getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument 2577 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument 2586 LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget) argument [all...] |
H A D | SparcTargetMachine.cpp | 65 Subtarget(TT, CPU, FS, *this, is64bit) {
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H A D | SparcInstrInfo.cpp | 37 Subtarget(ST) {} 312 if (Subtarget.isV9()) { 322 if (Subtarget.isV9()) { 323 if (Subtarget.hasHardQuad()) { 463 Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
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H A D | SparcFrameLowering.cpp | 246 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); local 248 const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); 277 Subtarget.getStackPointerBias();
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H A D | SparcISelDAGToDAG.cpp | 34 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can 36 const SparcSubtarget *Subtarget; member in class:__anon3003::SparcDAGToDAGISel 41 Subtarget = &MF.getSubtarget<SparcSubtarget>(); 71 unsigned GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF);
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/freebsd-11.0-release/contrib/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.h | 48 const NVPTXSubtarget *Subtarget; member in class:__anon2949::NVPTXDAGToDAGISel
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/freebsd-11.0-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZTargetMachine.cpp | 90 Subtarget(TT, CPU, FS, *this) {
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/freebsd-11.0-release/contrib/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.h | 45 const WebAssemblySubtarget *Subtarget; member in class:llvm::final
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/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 712 auto &HRI = *Subtarget.getRegisterInfo(); 775 if (NeedsArgAlign && Subtarget.hasV60TOps()) { 780 bool UseHVXDbl = Subtarget.useHVXDblOps(); 781 assert(Subtarget.useHVXOps()); 932 auto &HII = *Subtarget.getInstrInfo(); 978 const HexagonRegisterInfo *QRI = Subtarget.getRegisterInfo(); 1005 auto &HFI = *Subtarget.getFrameLowering(); 1054 bool UseHVX = Subtarget.useHVXOps(), UseHVXDbl = Subtarget.useHVXDblOps(); 1402 const HexagonRegisterInfo &HRI = *Subtarget [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64FrameLowering.cpp | 281 const AArch64Subtarget &Subtarget = MF->getSubtarget<AArch64Subtarget>(); local 282 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); 295 const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>(); local 296 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); 297 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 554 const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>(); local 555 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); 556 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
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H A D | AArch64InstrInfo.cpp | 33 RI(STI.getTargetTriple()), Subtarget(STI) {} 546 if (!Subtarget.isCortexA57() && !Subtarget.isCortexA53()) 996 unsigned char OpFlags = Subtarget.ClassifyGlobalReference(GV, TM); 1453 if (Subtarget.isCyclone()) { 1527 assert(Subtarget.hasNEON() && 1559 if (Subtarget.hasZeroCycleRegMove()) { 1580 } else if (SrcReg == AArch64::WZR && Subtarget.hasZeroCycleZeroing()) { 1584 if (Subtarget.hasZeroCycleRegMove()) { 1616 } else if (SrcReg == AArch64::XZR && Subtarget [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86TargetMachine.cpp | 112 Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) { 117 if (Subtarget.isTargetWin64())
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/freebsd-11.0-release/contrib/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.h | 97 const XCoreSubtarget &Subtarget); 144 const XCoreSubtarget &Subtarget; member in class:llvm::XCoreTargetLowering
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/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 244 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) { 351 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) { 379 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) { 383 } else if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS) { 388 } else if (Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS) { 532 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo()); 542 static_cast<const SIRegisterInfo*>(Subtarget->getRegisterInfo()); 576 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo()); 583 if (Subtarget->isAmdHsaOS() && Info->getShaderType() != ShaderType::COMPUTE) { 706 const unsigned Offset = Subtarget [all...] |