1//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the X86 specific subclass of TargetMachine.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86TargetMachine.h"
15#include "X86.h"
16#include "X86TargetObjectFile.h"
17#include "X86TargetTransformInfo.h"
18#include "llvm/CodeGen/Passes.h"
19#include "llvm/IR/Function.h"
20#include "llvm/IR/LegacyPassManager.h"
21#include "llvm/Support/CommandLine.h"
22#include "llvm/Support/FormattedStream.h"
23#include "llvm/Support/TargetRegistry.h"
24#include "llvm/Target/TargetOptions.h"
25using namespace llvm;
26
27static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
28                               cl::desc("Enable the machine combiner pass"),
29                               cl::init(true), cl::Hidden);
30
31namespace llvm {
32void initializeWinEHStatePassPass(PassRegistry &);
33}
34
35extern "C" void LLVMInitializeX86Target() {
36  // Register the target.
37  RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
38  RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
39
40  PassRegistry &PR = *PassRegistry::getPassRegistry();
41  initializeWinEHStatePassPass(PR);
42}
43
44static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
45  if (TT.isOSBinFormatMachO()) {
46    if (TT.getArch() == Triple::x86_64)
47      return make_unique<X86_64MachoTargetObjectFile>();
48    return make_unique<TargetLoweringObjectFileMachO>();
49  }
50
51  if (TT.isOSLinux() || TT.isOSNaCl())
52    return make_unique<X86LinuxNaClTargetObjectFile>();
53  if (TT.isOSBinFormatELF())
54    return make_unique<X86ELFTargetObjectFile>();
55  if (TT.isKnownWindowsMSVCEnvironment() || TT.isWindowsCoreCLREnvironment())
56    return make_unique<X86WindowsTargetObjectFile>();
57  if (TT.isOSBinFormatCOFF())
58    return make_unique<TargetLoweringObjectFileCOFF>();
59  llvm_unreachable("unknown subtarget type");
60}
61
62static std::string computeDataLayout(const Triple &TT) {
63  // X86 is little endian
64  std::string Ret = "e";
65
66  Ret += DataLayout::getManglingComponent(TT);
67  // X86 and x32 have 32 bit pointers.
68  if ((TT.isArch64Bit() &&
69       (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
70      !TT.isArch64Bit())
71    Ret += "-p:32:32";
72
73  // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
74  if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
75    Ret += "-i64:64";
76  else
77    Ret += "-f64:32:64";
78
79  // Some ABIs align long double to 128 bits, others to 32.
80  if (TT.isOSNaCl())
81    ; // No f80
82  else if (TT.isArch64Bit() || TT.isOSDarwin())
83    Ret += "-f80:128";
84  else
85    Ret += "-f80:32";
86
87  // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
88  if (TT.isArch64Bit())
89    Ret += "-n8:16:32:64";
90  else
91    Ret += "-n8:16:32";
92
93  // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
94  if (!TT.isArch64Bit() && TT.isOSWindows())
95    Ret += "-a:0:32-S32";
96  else
97    Ret += "-S128";
98
99  return Ret;
100}
101
102/// X86TargetMachine ctor - Create an X86 target.
103///
104X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
105                                   StringRef CPU, StringRef FS,
106                                   const TargetOptions &Options,
107                                   Reloc::Model RM, CodeModel::Model CM,
108                                   CodeGenOpt::Level OL)
109    : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
110                        OL),
111      TLOF(createTLOF(getTargetTriple())),
112      Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) {
113  // Windows stack unwinder gets confused when execution flow "falls through"
114  // after a call to 'noreturn' function.
115  // To prevent that, we emit a trap for 'unreachable' IR instructions.
116  // (which on X86, happens to be the 'ud2' instruction)
117  if (Subtarget.isTargetWin64())
118    this->Options.TrapUnreachable = true;
119
120  // By default (and when -ffast-math is on), enable estimate codegen for
121  // everything except scalar division. By default, use 1 refinement step for
122  // all operations. Defaults may be overridden by using command-line options.
123  // Scalar division estimates are disabled because they break too much
124  // real-world code. These defaults match GCC behavior.
125  this->Options.Reciprocals.setDefaults("sqrtf", true, 1);
126  this->Options.Reciprocals.setDefaults("divf", false, 1);
127  this->Options.Reciprocals.setDefaults("vec-sqrtf", true, 1);
128  this->Options.Reciprocals.setDefaults("vec-divf", true, 1);
129
130  initAsmInfo();
131}
132
133X86TargetMachine::~X86TargetMachine() {}
134
135const X86Subtarget *
136X86TargetMachine::getSubtargetImpl(const Function &F) const {
137  Attribute CPUAttr = F.getFnAttribute("target-cpu");
138  Attribute FSAttr = F.getFnAttribute("target-features");
139
140  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
141                        ? CPUAttr.getValueAsString().str()
142                        : TargetCPU;
143  std::string FS = !FSAttr.hasAttribute(Attribute::None)
144                       ? FSAttr.getValueAsString().str()
145                       : TargetFS;
146
147  // FIXME: This is related to the code below to reset the target options,
148  // we need to know whether or not the soft float flag is set on the
149  // function before we can generate a subtarget. We also need to use
150  // it as a key for the subtarget since that can be the only difference
151  // between two functions.
152  bool SoftFloat =
153      F.hasFnAttribute("use-soft-float") &&
154      F.getFnAttribute("use-soft-float").getValueAsString() == "true";
155  // If the soft float attribute is set on the function turn on the soft float
156  // subtarget feature.
157  if (SoftFloat)
158    FS += FS.empty() ? "+soft-float" : ",+soft-float";
159
160  auto &I = SubtargetMap[CPU + FS];
161  if (!I) {
162    // This needs to be done before we create a new subtarget since any
163    // creation will depend on the TM and the code generation flags on the
164    // function that reside in TargetOptions.
165    resetTargetOptions(F);
166    I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
167                                        Options.StackAlignmentOverride);
168  }
169  return I.get();
170}
171
172//===----------------------------------------------------------------------===//
173// Command line options for x86
174//===----------------------------------------------------------------------===//
175static cl::opt<bool>
176UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
177  cl::desc("Minimize AVX to SSE transition penalty"),
178  cl::init(true));
179
180//===----------------------------------------------------------------------===//
181// X86 TTI query.
182//===----------------------------------------------------------------------===//
183
184TargetIRAnalysis X86TargetMachine::getTargetIRAnalysis() {
185  return TargetIRAnalysis([this](const Function &F) {
186    return TargetTransformInfo(X86TTIImpl(this, F));
187  });
188}
189
190
191//===----------------------------------------------------------------------===//
192// Pass Pipeline Configuration
193//===----------------------------------------------------------------------===//
194
195namespace {
196/// X86 Code Generator Pass Configuration Options.
197class X86PassConfig : public TargetPassConfig {
198public:
199  X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
200    : TargetPassConfig(TM, PM) {}
201
202  X86TargetMachine &getX86TargetMachine() const {
203    return getTM<X86TargetMachine>();
204  }
205
206  void addIRPasses() override;
207  bool addInstSelector() override;
208  bool addILPOpts() override;
209  bool addPreISel() override;
210  void addPreRegAlloc() override;
211  void addPostRegAlloc() override;
212  void addPreEmitPass() override;
213  void addPreSched2() override;
214};
215} // namespace
216
217TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
218  return new X86PassConfig(this, PM);
219}
220
221void X86PassConfig::addIRPasses() {
222  addPass(createAtomicExpandPass(&getX86TargetMachine()));
223
224  TargetPassConfig::addIRPasses();
225}
226
227bool X86PassConfig::addInstSelector() {
228  // Install an instruction selector.
229  addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
230
231  // For ELF, cleanup any local-dynamic TLS accesses.
232  if (TM->getTargetTriple().isOSBinFormatELF() &&
233      getOptLevel() != CodeGenOpt::None)
234    addPass(createCleanupLocalDynamicTLSPass());
235
236  addPass(createX86GlobalBaseRegPass());
237
238  return false;
239}
240
241bool X86PassConfig::addILPOpts() {
242  addPass(&EarlyIfConverterID);
243  if (EnableMachineCombinerPass)
244    addPass(&MachineCombinerID);
245  return true;
246}
247
248bool X86PassConfig::addPreISel() {
249  // Only add this pass for 32-bit x86 Windows.
250  const Triple &TT = TM->getTargetTriple();
251  if (TT.isOSWindows() && TT.getArch() == Triple::x86)
252    addPass(createX86WinEHStatePass());
253  return true;
254}
255
256void X86PassConfig::addPreRegAlloc() {
257  if (getOptLevel() != CodeGenOpt::None)
258    addPass(createX86OptimizeLEAs());
259
260  addPass(createX86CallFrameOptimization());
261}
262
263void X86PassConfig::addPostRegAlloc() {
264  addPass(createX86FloatingPointStackifierPass());
265}
266
267void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
268
269void X86PassConfig::addPreEmitPass() {
270  if (getOptLevel() != CodeGenOpt::None)
271    addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
272
273  if (UseVZeroUpper)
274    addPass(createX86IssueVZeroUpperPass());
275
276  if (getOptLevel() != CodeGenOpt::None) {
277    addPass(createX86PadShortFunctions());
278    addPass(createX86FixupLEAs());
279  }
280}
281