| /freebsd-11.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 599 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
609 Regs.push_back(Reg + i);
643 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
645 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
654 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
659 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
724 unsigned NumRegs = Regs.size();
744 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
746 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
778 unsigned Flag = InlineAsm::getFlagWord(Code, Regs
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineScheduler.cpp | 347 // We want LiveOutRegs to contain only Regs whose content will be read after
1539 void SIScheduleBlockScheduler::addLiveRegs(std::set<unsigned> &Regs) { argument
1540 for (unsigned Reg : Regs) {
1550 std::set<unsigned> &Regs) {
1551 for (unsigned Reg : Regs) {
1549 decreaseLiveRegs(SIScheduleBlock *Block, std::set<unsigned> &Regs) argument
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| H A D | SIISelLowering.cpp | 754 SmallVector<SDValue, 4> Regs; local
755 Regs.push_back(Val);
761 Regs.push_back(Copy);
766 Regs.append(NumElements, DAG.getUNDEF(VT));
768 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
|
| /freebsd-11.0-release/contrib/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.h | 712 // Compute the set of registers completely covered by the registers in Regs.
713 // The returned BitVector will have a bit set for each register in Regs,
715 // registers in Regs.
719 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
|
| H A D | AsmMatcherEmitter.cpp | 2211 const auto &Regs = Target.getRegBank().getRegisters();
2212 for (const CodeGenRegister &Reg : Regs) {
|
| /freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/Disassembler/ |
| H A D | PPCDisassembler.cpp | 209 const unsigned (&Regs)[N]) {
211 Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
208 decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const unsigned (&Regs)[N]) argument
|
| /freebsd-11.0-release/contrib/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 2425 unsigned Regs[2];
2452 Regs[FoundRegs++] = Candidate;
2462 Regs[FoundRegs++] = Regs[0];
2466 TII.get(STI.is64Bit() ? X86::POP64r : X86::POP32r), Regs[i]);
|
| H A D | X86ISelLowering.cpp | [all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 1242 CreateRegList(SmallVectorImpl<unsigned> &Regs, SMLoc StartLoc, SMLoc EndLoc, argument
1244 assert (Regs.size() > 0 && "Empty list not allowed");
1247 Op->RegList.List = new SmallVector<unsigned, 10>(Regs.begin(), Regs.end());
4484 SmallVector<unsigned, 10> Regs; local
4503 Regs.push_back(RegNo);
4515 Regs.push_back(TmpReg++);
4542 Regs.push_back(RegNo);
4562 Operands.push_back(MipsOperand::CreateRegList(Regs, S, E, *this));
4587 SmallVector<unsigned, 10> Regs; local
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 2009 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
2026 Inst.addOperand(MCOperand::createReg(Regs[i]));
2037 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
2051 Inst.addOperand(MCOperand::createReg(Regs[i]));
|
| /freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitSimplify.cpp | 971 SmallVector<unsigned,2> Regs;
980 Regs.push_back(R);
986 for (unsigned i = 0, n = Regs.size(); i != n; ++i)
987 MRI.markUsesInDebugValueAsUndef(Regs[i]);
|
| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2607 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs, argument
2609 assert (Regs.size() > 0 && "RegList contains no registers?");
2612 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2615 contains(Regs.front().second))
2619 array_pod_sort(Regs.begin(), Regs.end());
2623 I = Regs.begin(), E = Regs.end(); I != E; ++I)
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