Lines Matching refs:Regs
599 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
609 Regs.push_back(Reg + i);
643 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
645 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
654 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
659 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
724 unsigned NumRegs = Regs.size();
744 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
746 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
778 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
781 else if (!Regs.empty() &&
782 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
789 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
801 assert(Reg < Regs.size() && "Mismatch in # registers expected");
802 unsigned TheReg = Regs[Reg++];
6046 SmallVector<unsigned, 4> Regs;
6101 Regs.push_back(AssignedReg);
6103 // If this is an expanded reference, add the rest of the regs to Regs.
6113 Regs.push_back(*I);
6117 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6131 Regs.push_back(RegInfo.createVirtualRegister(RC));
6133 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6415 if (OpInfo.AssignedRegs.Regs.empty()) {
6487 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6582 if (OpInfo.AssignedRegs.Regs.empty()) {
6602 if (!OpInfo.AssignedRegs.Regs.empty())
6621 if (!RetValRegs.Regs.empty()) {