/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/builtins/aarch64/ |
H A D | fp_mode.c | 16 #define AARCH64_TOWARDZERO 0x3
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrFoldTables.h | 61 TB_BCAST_MASK = 0x3 << TB_BCAST_TYPE_SHIFT,
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/freebsd-11-stable/stand/i386/gptboot/ |
H A D | Makefile | 12 B2SIOFMT?= 0x3
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/freebsd-11-stable/stand/i386/isoboot/ |
H A D | Makefile | 13 B2SIOFMT?= 0x3
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/freebsd-11-stable/stand/i386/zfsboot/ |
H A D | Makefile | 12 B2SIOFMT?= 0x3
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/freebsd-11-stable/stand/i386/gptzfsboot/ |
H A D | Makefile | 14 B2SIOFMT?= 0x3
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/freebsd-11-stable/sys/amd64/vmm/ |
H A D | x86.h | 35 #define CPUID_0000_0003 (0x3)
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/freebsd-11-stable/contrib/llvm-project/clang/lib/Headers/ |
H A D | opencl-c-base.h | 396 #define CL_QUEUED 0x3 439 #define CLK_AVC_ME_MAJOR_8x8_INTEL 0x3 444 #define CLK_AVC_ME_MINOR_4x4_INTEL 0x3 466 #define CLK_AVC_ME_SEARCH_WINDOW_EXTRA_TINY_INTEL 0x3 478 #define CLK_AVC_ME_SUBPIXEL_MODE_QPEL_INTEL 0x3 483 #define CLK_AVC_ME_COST_PRECISION_DPEL_INTEL 0x3 505 #define CLK_AVC_ME_SKIP_BLOCK_16x16_DUAL_ENABLE_INTEL (0x3 << 24) 524 #define CLK_AVC_ME_INTRA_LUMA_PARTITION_MASK_4x4_INTEL 0x3 534 #define CLK_AVC_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_LEFT_INTEL 0x3 544 #define CLK_AVC_ME_CHROMA_PREDICTOR_MODE_PLANE_INTEL 0x3 [all...] |
/freebsd-11-stable/sys/arm/ti/ |
H A D | ti_sdma.h | 49 #define TI_SDMA_BURST_64 0x3 58 #define TI_SDMA_ADDR_DOUBLE_INDEX 0x3
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/freebsd-11-stable/sys/contrib/ncsw/inc/ |
H A D | types_freebsd.h | 71 #define QE_32_BIT_SHIFT8(__arg) (uint32_t)((3 - ((uint32_t)&(__arg) & 0x3)) * 8) 72 #define QE_32_BIT_SHIFT16(__arg) (uint32_t)((2 - ((uint32_t)&(__arg) & 0x3)) * 8)
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/freebsd-11-stable/crypto/heimdal/base/ |
H A D | baselocl.h | 114 #define heim_base_is_tagged(x) (((uintptr_t)(x)) & 0x3) 116 #define heim_base_is_tagged_object(x) ((((uintptr_t)(x)) & 0x3) == 1)
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/freebsd-11-stable/sys/mips/nlm/ |
H A D | board_cpld.c | 45 #define CPLD_RSVD 0x3 112 return (val & 0x3);
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/freebsd-11-stable/sys/mips/nlm/hal/ |
H A D | nlm_hal.c | 52 pll_divr = ((rstval >> 8) & 0x3) + 1; 54 ext_div = ((rstval >> 30) & 0x3) + 1;
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/freebsd-11-stable/sys/dev/etherswitch/e6000sw/ |
H A D | e6000swreg.h | 61 #define SWITCH_ID 0x3 75 #define PORT_CONTROL_ENABLE 0x3
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/freebsd-11-stable/sys/isa/ |
H A D | pnpreg.h | 230 #define PNP_TAG_COMPAT_DEVICE 0x3 244 #define PNP_TAG_ID_UNICODE 0x3
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/freebsd-11-stable/sys/dev/sfxge/common/ |
H A D | efx_regs_mcdi.h | 396 #define MCDI_EVENT_LEVEL_FATAL 0x3 413 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 443 #define MCDI_EVENT_TX_ERR_2BIG 0x3 463 #define MCDI_EVENT_PTP_ERR_FIFO 0x3 473 #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 515 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3 555 #define MCDI_EVENT_MUM_WATCHDOG 0x3 573 #define MCDI_EVENT_CODE_CMDDONE 0x3 738 #define FCDI_EVENT_LEVEL_FATAL 0x3 757 #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 [all...] |
/freebsd-11-stable/sys/arm/allwinner/clk/ |
H A D | aw_ahbclk.c | 52 #define A10_AHB_CLK_DIV_RATIO (0x3 << 4) 55 #define A13_AHB_CLK_SRC_SEL (0x3 << 6) 59 #define A31_AHB1_PRE_DIV (0x3 << 6) 61 #define A31_AHB1_CLK_SRC_SEL (0x3 << 12) 66 #define A83T_AHB1_CLK_SRC_SEL (0x3 << 12) 70 #define A83T_AHB1_PRE_DIV (0x3 << 6) 72 #define A83T_AHB1_CLK_DIV_RATIO (0x3 << 4) 75 #define H3_AHB2_CLK_CFG (0x3 << 0)
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H A D | aw_apbclk.c | 52 #define A10_APB0_CLK_RATIO (0x3 << 8) 54 #define A10_APB1_CLK_SRC_SEL (0x3 << 24) 56 #define A10_APB1_CLK_SRC_SEL_MAX 0x3 57 #define A10_APB1_CLK_RAT_N (0x3 << 16) 61 #define A23_APB0_CLK_RATIO (0x3 << 0) 63 #define A83T_APB1_CLK_RATIO (0x3 << 8)
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/freebsd-11-stable/sys/netgraph/bluetooth/include/ |
H A D | ng_btsocket_rfcomm.h | 79 #define RFCOMM_RPN_BR_9600 0x3 90 #define RFCOMM_RPN_DATA_8 0x3 208 #define RFCOMM_RPN_DATA_BITS(line) ((line) & 0x3) 210 #define RFCOMM_RPN_PARITY(line) (((line) >> 3) & 0x3) 212 (((data) & 0x3) | (((stop) & 0x1) << 2) | (((parity) & 0x3) << 3))
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/freebsd-11-stable/sys/dev/qlnx/qlnxe/ |
H A D | common_hsi.h | 825 #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3 /* This value will determine the RX FSM timer resolution in ticks */ 827 #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3 /* This value will determine the TX FSM timer resolution in ticks */ 857 #define CORE_DB_DATA_DEST_MASK 0x3 /* destination of doorbell (use enum db_dest) */ 859 #define CORE_DB_DATA_AGG_CMD_MASK 0x3 /* aggregative command to CM (use enum db_agg_cmd_sel) */ 865 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3 /* aggregative value selection */ 921 #define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3 /* Type of DPM transaction (DPM_L2_INLINE or DPM_L2_BD) (use enum db_dpm_type) */ 946 #define DB_L2_DPM_SGE_RESERVED0_MASK 0x3 962 #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3 981 #define DB_PWM_ADDR_WID_MASK 0x3 /* Window ID */ 998 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3 /* Typ [all...] |
/freebsd-11-stable/sys/arm64/arm64/ |
H A D | exception.S | 55 stp x2, x3, [sp, #(TF_X + 2 * 8)] 86 ldp x2, x3, [sp, #(TF_X + 2 * 8)] 127 mov x3, #((TDF_ASTPENDING|TDF_NEEDRESCHED) >> 8) 128 lsl x3, x3, #8 129 and x2, x2, x3
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/freebsd-11-stable/sys/arm/nvidia/drm2/ |
H A D | tegra_hdmi_reg.h | 43 #define SOR_STATE1_ASY_HEAD_OPMODE(x) (((x) & 0x3) << 0) 55 #define SOR_STATE2_ASY_CRCMODE(x) (((x) & 0x3) << 6) 59 #define SOR_STATE2_ASY_SUBOWNER(x) (((x) & 0x3) << 4) 64 #define SOR_STATE2_ASY_OWNER(x) (((x) & 0x3) << 0) 185 #define SOR_CSTM_MODE(x) (((x) & 0x3) << 12) 211 #define SOR_SEQ_INST_WAIT_UNITS(x) (((x) & 0x3) << 12)
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/freebsd-11-stable/sys/gnu/dts/arm/ |
H A D | imx35-pinfunc.h | 20 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0 26 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0 30 #define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE 0x00c 0x330 0x000 0x3 0x0 38 #define MX35_PAD_GPIO1_1__CSPI1_SS2 0x014 0x338 0x7d8 0x3 0x0 126 #define MX35_PAD_CS1__EMI_NANDF_CE3 0x0a4 0x47c 0x000 0x3 0x0 131 #define MX35_PAD_CS4__EMI_NANDF_CE1 0x0b0 0x488 0x000 0x3 0x0 136 #define MX35_PAD_CS5__EMI_NANDF_CE2 0x0b4 0x48c 0x000 0x3 0x0 289 #define MX35_PAD_HCKR__IPU_FLASH_STROBE 0x148 0x58c 0x000 0x3 0x0 308 #define MX35_PAD_TX5_RX0__CAN2_TXCAN 0x158 0x59c 0x000 0x3 0x0 315 #define MX35_PAD_TX4_RX1__CAN2_RXCAN 0x15c 0x5a0 0x7cc 0x3 [all...] |
/freebsd-11-stable/sys/dev/bxe/ |
H A D | ecore_hsi.h | 2470 #define LFA_DUPLEX_MISMATCH 0x3 3591 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF (0x3<<14) /* BitField agg_vars1Various aggregative variables Aux 4 counter flag */ 3593 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66 (0x3<<16) /* BitField agg_vars1Various aggregative variables The connection QOS */ 3607 #define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE (0x3<<26) /* BitField agg_vars1Various aggregative variables 0-NOP, 1-EQ, 2-NEQ */ 3609 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52 (0x3<<28) /* BitField agg_vars1Various aggregative variables 0-NOP, 1-EQ, 2-NEQ */ 3611 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53 (0x3<<30) /* BitField agg_vars1Various aggregative variables 0-NOP, 1-EQ, 2-NEQ */ 3735 #define DMAE_CMD_DST (0x3<<1) /* BitField opcode The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */ 3745 #define DMAE_CMD_ENDIANITY (0x3<<9) /* BitField opcode swapping mode. */ 3755 #define DMAE_CMD_E1HVN (0x3<<15) /* BitField opcode vnic number E2 and onwards source vnic */ 3757 #define DMAE_CMD_DST_VN (0x3<<1 [all...] |
/freebsd-11-stable/sys/dev/ce/ |
H A D | tau32-ddk.c | 202 MiEVK2:0x3;unsigned vkd5K4:01;unsigned:01;unsigned k18ZY3:5;unsigned: 237 yA8D32:3;unsigned YcoYR3:3;unsigned kz_Xg4:0x3;unsigned a17ei2:0x3; 278 ;unsigned KYiBO3:0x1;unsigned WtICk3:0x1;unsigned:0x3;unsigned:010; 376 <<2),~(0x1ul<<0x3),~(01ul<<04),~(1ul<<5),~(01ul<<06),~(1ul<<7),~( 1073 kvYKl=0;Vl2C45=(256*2) *0x3;{VlZ2k:{IxW_32 mlK913;{if(!(010))goto 1479 0xFFu);Ae0Cg2(0x1,RdZoN,kKiv65+0x3,vgKFx2>>24);}__noinline static 1483 +=_ozJC4(01,RdZoN,kKiv65+0x3)<<0x18;return Kt5Iv1;}__noinline static 1704 +=((rx55l1&0x3)<<8)+fFvjz3(RdZoN,3);bgpE63:;}tYsSE2=fFvjz3(RdZoN,4);{ 1708 0x3)<< [all...] |