1289947Szbb/*- 2289947Szbb * Copyright (c) 2015 Semihalf 3289947Szbb * Copyright (c) 2015 Stormshield 4289947Szbb * All rights reserved. 5289947Szbb * 6289947Szbb * Redistribution and use in source and binary forms, with or without 7289947Szbb * modification, are permitted provided that the following conditions 8289947Szbb * are met: 9289947Szbb * 1. Redistributions of source code must retain the above copyright 10289947Szbb * notice, this list of conditions and the following disclaimer. 11289947Szbb * 2. Redistributions in binary form must reproduce the above copyright 12289947Szbb * notice, this list of conditions and the following disclaimer in the 13289947Szbb * documentation and/or other materials provided with the distribution. 14289947Szbb * 15289947Szbb * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16289947Szbb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17289947Szbb * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18289947Szbb * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19289947Szbb * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20289947Szbb * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21289947Szbb * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22289947Szbb * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23289947Szbb * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24289947Szbb * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25289947Szbb * SUCH DAMAGE. 26289947Szbb * 27289947Szbb * $FreeBSD$ 28289947Szbb * 29289947Szbb */ 30289947Szbb 31289947Szbb#ifndef _E6000SWREG_H_ 32289947Szbb#define _E6000SWREG_H_ 33289947Szbb 34289947Szbbstruct atu_opt { 35289947Szbb uint16_t mac_01; 36289947Szbb uint16_t mac_23; 37289947Szbb uint16_t mac_45; 38289947Szbb uint16_t fid; 39289947Szbb}; 40289947Szbb 41289947Szbb/* 42289947Szbb * Definitions for the Marvell 88E6000 series Ethernet Switch. 43289947Szbb */ 44289947Szbb 45289947Szbb#define CPU_PORT 0x5 46289947Szbb 47289947Szbb/* 48289947Szbb * Switch Registers 49289947Szbb */ 50289947Szbb#define REG_GLOBAL 0x1b 51289947Szbb#define REG_GLOBAL2 0x1c 52289947Szbb#define REG_PORT(p) (0x10 + (p)) 53289947Szbb 54289947Szbb#define REG_NUM_MAX 31 55289947Szbb 56289947Szbb/* 57289947Szbb * Per-Port Switch Registers 58289947Szbb */ 59289947Szbb#define PORT_STATUS 0x0 60289947Szbb#define PSC_CONTROL 0x1 61289947Szbb#define SWITCH_ID 0x3 62289947Szbb#define PORT_CONTROL 0x4 63289947Szbb#define PORT_CONTROL_1 0x5 64289947Szbb#define PORT_VLAN_MAP 0x6 65289947Szbb#define PORT_VID 0x7 66289947Szbb#define PORT_ASSOCIATION_VECTOR 0xb 67289947Szbb#define PORT_ATU_CTRL 0xc 68289947Szbb#define RX_COUNTER 0x12 69289947Szbb#define TX_COUNTER 0x13 70289947Szbb 71289947Szbb#define PORT_VID_DEF_VID 0 72289947Szbb#define PORT_VID_DEF_VID_MASK 0xfff 73289947Szbb#define PORT_VID_PRIORITY_MASK 0xc00 74289947Szbb 75289947Szbb#define PORT_CONTROL_ENABLE 0x3 76289947Szbb 77289947Szbb/* PORT_VLAN fields */ 78289947Szbb#define PORT_VLAN_MAP_TABLE_MASK 0x7f 79289947Szbb#define PORT_VLAN_MAP_FID 12 80289947Szbb#define PORT_VLAN_MAP_FID_MASK 0xf000 81289947Szbb/* 82289947Szbb * Switch Global Register 1 accessed via REG_GLOBAL_ADDR 83289947Szbb */ 84289947Szbb#define SWITCH_GLOBAL_STATUS 0 85289947Szbb#define SWITCH_GLOBAL_CONTROL 4 86289947Szbb#define SWITCH_GLOBAL_CONTROL2 28 87289947Szbb 88289947Szbb#define MONITOR_CONTROL 26 89289947Szbb 90289947Szbb/* ATU operation */ 91289947Szbb#define ATU_FID 1 92289947Szbb#define ATU_CONTROL 10 93289947Szbb#define ATU_OPERATION 11 94289947Szbb#define ATU_DATA 12 95289947Szbb#define ATU_MAC_ADDR01 13 96289947Szbb#define ATU_MAC_ADDR23 14 97289947Szbb#define ATU_MAC_ADDR45 15 98289947Szbb 99289947Szbb#define ATU_UNIT_BUSY (1 << 15) 100289947Szbb#define ENTRY_STATE 0xf 101289947Szbb 102289947Szbb/* ATU_CONTROL fields */ 103289947Szbb#define ATU_CONTROL_AGETIME 4 104289947Szbb#define ATU_CONTROL_AGETIME_MASK 0xff0 105289947Szbb#define ATU_CONTROL_LEARN2ALL 3 106289947Szbb 107289947Szbb/* ATU opcode */ 108289947Szbb#define NO_OPERATION (0 << 0) 109289947Szbb#define FLUSH_ALL (1 << 0) 110289947Szbb#define FLUSH_NON_STATIC (1 << 1) 111289947Szbb#define LOAD_FROM_FIB (3 << 0) 112289947Szbb#define PURGE_FROM_FIB (3 << 0) 113289947Szbb#define GET_NEXT_IN_FIB (1 << 2) 114289947Szbb#define FLUSH_ALL_IN_FIB (5 << 0) 115289947Szbb#define FLUSH_NON_STATIC_IN_FIB (3 << 1) 116289947Szbb#define GET_VIOLATION_DATA (7 << 0) 117289947Szbb#define CLEAR_VIOLATION_DATA (7 << 0) 118289947Szbb 119289947Szbb/* ATU Stats */ 120289947Szbb#define COUNT_ALL (0 << 0) 121289947Szbb 122289947Szbb/* 123289947Szbb * Switch Global Register 2 accessed via REG_GLOBAL2_ADDR 124289947Szbb */ 125289947Szbb#define MGMT_EN_2x 2 126289947Szbb#define MGMT_EN_0x 3 127289947Szbb#define SWITCH_MGMT 5 128289947Szbb#define ATU_STATS 14 129289947Szbb 130289947Szbb#define MGMT_EN_ALL 0xffff 131289947Szbb 132289947Szbb/* SWITCH_MGMT fields */ 133289947Szbb 134289947Szbb#define SWITCH_MGMT_PRI 0 135289947Szbb#define SWITCH_MGMT_PRI_MASK 7 136289947Szbb#define SWITCH_MGMT_RSVD2CPU 3 137289947Szbb#define SWITCH_MGMT_FC_PRI 4 138289947Szbb#define SWITCH_MGMT_FC_PRI_MASK (7 << 4) 139289947Szbb#define SWITCH_MGMT_FORCEFLOW 7 140289947Szbb 141289947Szbb/* ATU_STATS fields */ 142289947Szbb 143289947Szbb#define ATU_STATS_BIN 14 144289947Szbb#define ATU_STATS_FLAG 12 145289947Szbb 146289947Szbb/* 147289947Szbb * PHY registers accessed via 'Switch Global Registers' (REG_GLOBAL2). 148289947Szbb */ 149289947Szbb#define SMI_PHY_CMD_REG 0x18 150289947Szbb#define SMI_PHY_DATA_REG 0x19 151289947Szbb 152289947Szbb#define PHY_CMD 0x18 153289947Szbb#define PHY_DATA 0x19 154289947Szbb#define PHY_DATA_MASK 0xffff 155289947Szbb 156289947Szbb#define PHY_CMD_SMI_BUSY 15 157289947Szbb#define PHY_CMD_MODE 12 158289947Szbb#define PHY_CMD_MODE_MDIO 1 159289947Szbb#define PHY_CMD_MODE_XMDIO 0 160289947Szbb#define PHY_CMD_OPCODE 10 161289947Szbb#define PHY_CMD_OPCODE_WRITE 1 162289947Szbb#define PHY_CMD_OPCODE_READ 2 163289947Szbb#define PHY_CMD_DEV_ADDR 5 164289947Szbb#define PHY_CMD_DEV_ADDR_MASK 0x3e0 165289947Szbb#define PHY_CMD_REG_ADDR 0 166289947Szbb#define PHY_CMD_REG_ADDR_MASK 0x1f 167289947Szbb 168289947Szbb#define PHY_PAGE_REG 22 169289947Szbb 170289947Szbb#define E6000SW_NUM_PHYS 5 171289947Szbb#define E6000SW_NUM_PHY_REGS 29 172289947Szbb#define E6000SW_CPUPORTS_MASK ((1 << 5) | (1 << 6)) 173289947Szbb#define E6000SW_NUM_VGROUPS 8 174289947Szbb#define E6000SW_NUM_PORTS 7 175289947Szbb#define E6000SW_PORT_NO_VGROUP -1 176289947Szbb#define E6000SW_DEFAULT_AGETIME 20 177289947Szbb#define E6000SW_RETRIES 100 178289947Szbb 179289947Szbb 180289947Szbb/* Default vlangroups */ 181289947Szbb#define E6000SW_DEF_VLANGROUP0 (1 | (1 << 1) | (1 << 2) | (1 << 3) | \ 182289947Szbb (1 << 6)) 183289947Szbb#define E6000SW_DEF_VLANGROUP1 ((1 << 4) | (1 << 5)) 184289947Szbb 185289947Szbb#endif /* _E6000SWREG_H_ */ 186