Searched refs:i8 (Results 26 - 50 of 91) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Support/
H A DMachineValueType.h41 i8 = 3, // This is an 8 bit integer value
72 v1i8 = 25, // 1 x i8
73 v2i8 = 26, // 2 x i8
74 v4i8 = 27, // 4 x i8
75 v8i8 = 28, // 8 x i8
76 v16i8 = 29, // 16 x i8
77 v32i8 = 30, // 32 x i8
78 v64i8 = 31, // 64 x i8
79 v128i8 = 32, //128 x i8
80 v256i8 = 33, //256 x i8
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp119 // X86 is weird. It always uses i8 for shift amounts and setcc results.
173 addRegisterClass(MVT::i8, &X86::GR8RegClass);
185 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
187 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
188 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
218 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
219 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i8, Promote);
231 // Promote i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
233 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
234 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i8, Promot
[all...]
H A DX86ISelDAGToDAG.cpp408 /// Return a target constant with the specified value of type i8.
410 return CurDAG->getTargetConstant(Imm, DL, MVT::i8);
931 CurDAG->getTargetConstant(Imm, dl, MVT::i8)});
935 CurDAG->getTargetConstant(Imm, dl, MVT::i8));
1647 SDValue Eight = DAG.getConstant(8, DL, MVT::i8);
1651 SDValue ShlCount = DAG.getConstant(ScaleLog, DL, MVT::i8);
1829 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, DL, MVT::i8);
1831 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, DL, MVT::i8);
1884 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, DL, MVT::i8);
1888 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, DL, MVT::i8);
[all...]
H A DX86TargetTransformInfo.cpp858 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/
862 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/
1965 { ISD::BITREVERSE, MVT::i8, 3 }
2121 { ISD::CTLZ, MVT::i8, 1 },
2129 { ISD::CTPOP, MVT::i8, 1 },
2141 { ISD::BITREVERSE, MVT::i8, 11 },
2144 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV
2147 { ISD::CTPOP, MVT::i8, 7 },
2150 { ISD::SADDO, MVT::i8, 1 },
2153 { ISD::UADDO, MVT::i8,
[all...]
H A DX86InterleavedAccess.cpp366 MVT VT = MVT::getVectorVT(MVT::i8, NumOfElm);
643 MVT VT = MVT::getVectorVT(MVT::i8, VecElems);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp333 case MVT::i8:
1000 /// simple value type such as i1, i8, and i16.
1010 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
1171 case MVT::i8:
1496 case MVT::i8:
1684 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) {
1685 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1708 case MVT::i8:
1730 if (RetVT >= MVT::i8 && RetVT <= MVT::i16 && ISDOpc != ISD::AND) {
1731 uint64_t Mask = (RetVT == MVT::i8)
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp125 case MVT::i8:
453 case MVT::i8:
483 case MVT::i8:
663 case MVT::i8:
774 case MVT::i8:
910 case MVT::i8:
1173 case MVT::i8:
1231 case MVT::i8:
1319 case MVT::i8:
/freebsd-11-stable/secure/lib/libcrypto/arm/
H A Dghashv8-armx.S13 vmov.i8 q11,#0xe1
63 vmov.i8 q11,#0xe1
121 vmov.i8 q11,#0xe1
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp306 case MVT::i8:
334 case MVT::i8:
H A DMSP430ISelLowering.h79 return MVT::i8;
111 /// register R15W to i8 by referencing its sub-register R15B.
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.cpp90 if (TRI->isTypeLegalForClass(*RC, MVT::i8)) {
H A DAVRInstrInfo.cpp144 if (TRI->isTypeLegalForClass(*RC, MVT::i8)) {
178 if (TRI->isTypeLegalForClass(*RC, MVT::i8)) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.h226 static MVT Types[] = { MVT::i8, MVT::i16, MVT::i32 };
H A DHexagonISelLowering.cpp608 bool IsLegalType = VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
911 if (OpTy == MVT::i8 || OpTy == MVT::i16) {
1365 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
1369 setOperationAction(ISD::SETCC, MVT::i8, Custom);
1406 setOperationAction(ISD::CTLZ, MVT::i8, Promote);
1408 setOperationAction(ISD::CTTZ, MVT::i8, Promote);
1412 setOperationAction(ISD::CTPOP, MVT::i8, Promote);
1521 // Extending loads from (native) vectors of i8 into (native) vectors of i16
1573 // Custom-lower bitcasts from i8 to v8i1.
1574 setOperationAction(ISD::BITCAST, MVT::i8, Custo
[all...]
/freebsd-11-stable/contrib/binutils/opcodes/
H A Darm-dis.c597 {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
3446 unsigned int i8 = (given & 0x000000ff);
3457 unsigned int Rm = (i8 & 0x0f);
3458 unsigned int sh = (i8 & 0x30) >> 4;
3468 offset = i8;
3472 offset = -i8;
3476 offset = i8;
3481 offset = -i8;
3486 offset = i8;
3491 offset = -i8;
3445 unsigned int i8 = (given & 0x000000ff); local
[all...]
/freebsd-11-stable/contrib/ntp/sntp/libevent/test/
H A Dregress_util.c695 ev_int8_t i8; local
711 tt_int_op(sizeof(i8), ==, 1);
755 i8 = EV_INT8_MAX;
757 tt_assert(i8 > 0);
759 /* i8++;*/
761 /* tt_assert(i8 == EV_INT8_MIN); */
762 /* tt_assert(i8 < 0); */
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp201 return (BytesLeft >= 2) ? MVT::i16 : MVT::i8;
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h336 return EVT(MVT::i8);
/freebsd-11-stable/crypto/openssl/crypto/aes/asm/
H A Dbsaes-armv7.pl676 vmov.i8 $t0,#0x55 @ compose .LBS0
677 vmov.i8 $t1,#0x33 @ compose .LBS1
682 vmov.i8 $t0,#0x0f @ compose .LBS2
931 vmov.i8 @XMM[8], #0x01 @ bit masks
932 vmov.i8 @XMM[9], #0x02
933 vmov.i8 @XMM[10], #0x04
934 vmov.i8 @XMM[11], #0x08
935 vmov.i8 @XMM[12], #0x10
936 vmov.i8 @XMM[13], #0x20
951 vmov.i8
[all...]
H A Daesv8-armx.pl159 vmov.i8 $key,#8 // borrow $key
161 vsub.i8 $mask,$mask,$key // adjust the mask
905 s/vmov\.i8/movi/o or # fix up legacy mnemonics
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp428 // build_vector lo, (zextload ptr from i8) -> load_d16_hi_u8 ptr, lo
429 // build_vector lo, (sextload ptr from i8) -> load_d16_hi_i8 ptr, lo
442 if (LdHi->getMemoryVT() == MVT::i8) {
460 // build_vector (zextload ptr from i8), hi -> load_d16_lo_u8 ptr, hi
461 // build_vector (sextload ptr from i8), hi -> load_d16_lo_i8 ptr, hi
470 if (LdLo->getMemoryVT() == MVT::i8) {
1272 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
1273 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
1307 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
1308 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
[all...]
H A DR600ISelLowering.cpp80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Custom);
84 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom);
88 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Custom);
101 setOperationAction(ISD::STORE, MVT::i8, Custom);
106 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
192 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1142 //TODO: Who creates the i8 stores?
1144 || Store->getValue().getValueType() == MVT::i8);
1148 if (Store->getMemoryVT() == MVT::i8) {
1279 if (MemVT == MVT::i8) {
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp128 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
190 case MVT::i8:
960 if (N->getMemoryVT() == MVT::i8)
962 N->getBasePtr(), N->getPointerInfo(), MVT::i8,
990 if (N->getMemoryVT() == MVT::i8)
992 N->getBasePtr(), N->getPointerInfo(), MVT::i8,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp397 for (MVT VT : {MVT::f16, MVT::v2f16, MVT::f32, MVT::f64, MVT::i1, MVT::i8,
408 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
431 setOperationAction(ISD::ROTL, MVT::i8, Expand);
432 setOperationAction(ISD::ROTR, MVT::i8, Expand);
492 // Custom handling for i8 intrinsics
493 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
1334 // i8 types in IR will be i16 types in SDAG
1336 (getValueType(DL, Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
2247 // v1 = ld i8* addr (-> i16)
2340 // Therefore, we must ensure the type is legal. For i1 and i8, w
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
128 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);

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