Searched refs:i1 (Results 151 - 175 of 184) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp2827 if (VT == MVT::i1)
2833 // An extended value of 1 is always true, unless its original type is i1,
2835 return (N->isOne() && !SExt) || (SExt && (N->getValueType(0) != MVT::i1));
3102 // The shift would not be valid if the operands are boolean (i1).
3265 return DAG.getSetCC(dl, VT, Trunc, DAG.getConstant(0, dl, MVT::i1),
3282 if (TopSetCC.getValueType() == MVT::i1 && VT == MVT::i1 &&
3450 (N0.getValueType() == MVT::i1 ||
3502 // Ensure that the input setccs return an i1 type or 0/1 value.
3503 if (Op0.getValueType() == MVT::i1 ||
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H A DSelectionDAGBuilder.cpp485 // Handle cases such as i8 -> <1 x i1>
2382 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, CondRHS, CB.CC);
2394 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
2399 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
4634 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
6397 EVT CCVT = MVT::i1;
6647 EVT OverflowVT = MVT::i1;
7403 SDValue Cmp = DAG.getSetCC(getCurSDLoc(), MVT::i1, LoadL, LoadR, ISD::SETNE);
10139 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
H A DLegalizeDAG.cpp550 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
729 // Some targets pretend to have an i1 loading operation, and actually
735 // Until such a way is found, don't insist on promoting i1 here.
736 (SrcVT != MVT::i1 ||
737 TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) ==
2608 // and finally the i1 pairs.
2636 // swap i1: ((V & 0xAA) >> 1) | ((V & 0x55) << 1)
3461 DAG.getZeroExtendInReg(DAG.getZExtOrTrunc(Carry, dl, VT), dl, MVT::i1);
3587 // We test only the i1 bit. Skip the AND if UNDEF or another AND.
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DSimplifyCFG.cpp775 unsigned i1 = 0, i2 = 0, e1 = V1->size(), e2 = V2->size(); local
776 while (i1 != e1 && i2 != e2) {
777 if ((*V1)[i1].Value == (*V2)[i2].Value)
779 if ((*V1)[i1].Value < (*V2)[i2].Value)
780 ++i1;
1873 /// br i1 %cmp, label %EndBB, label %ThenBB
1884 /// %add.add5 = select i1 %cmp, i32 %add, %add5
1943 /// br i1 %cmp, label %EndBB, label %ThenBB
1957 /// %cond = select i1 %cmp, 0, %sub
2366 // Don't fold i1 branche
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp289 // We have native instructions for i8, i16 and i32 extensions, but not i1.
290 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
292 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
293 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
294 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
3632 if (N->getValueType(1) == MVT::i1)
3633 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC);
3698 if (N->getValueType(1) == MVT::i1)
3699 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC);
5615 // Convert (sext_in_reg (setcc LHS, RHS, COND), i1)
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp578 // AArch64 does not have floating-point extending loads, i1 sign-extending
587 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand);
1908 /// Tries to transform the given i1 producing node @p Val to a series compare
3363 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
3364 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
3416 RegVT.getVectorElementType() == MVT::i1)
3985 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
3986 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
4074 if (Outs[i].ArgVT == MVT::i1) {
4075 // AAPCS requires i1 t
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp118 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
123 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
128 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
206 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
1701 SDValue Zero1 = DAG.getConstant(0, DL, MVT::i1);
1702 SDVTList HalfCarryVT = DAG.getVTList(HalfVT, MVT::i1);
/freebsd-11-stable/tools/tools/net80211/wesside/wesside/
H A Dwesside.c1656 unsigned char* m1, unsigned char* i1,
1664 inet_aton(i1, &sip);
1655 do_arp(unsigned char* buf, unsigned short op, unsigned char* m1, unsigned char* i1, unsigned char* m2, unsigned char* i2) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1157 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1174 IntReg >= (unsigned)MVT::i1; --IntReg) {
1385 // <4 x i1> -> <4 x i32>.
H A DMachinePipeliner.cpp2678 auto CompareKey = [](UnitIndex i1, UnitIndex i2) {
2679 return std::get<0>(i1) < std::get<0>(i2);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
243 // - i1 extending loads.
249 setLoadExtAction(Ext, T, MVT::i1, Promote);
/freebsd-11-stable/contrib/binutils/bfd/
H A Delfxx-ia64.c854 bfd_vma t0, t1, i0, i1, i2;
864 i1 = 0x4000000000LL;
874 t0 = (i1 << 46) | (i0 << 5) | template;
875 t1 = (i2 << 23) | (i1 >> 18);
852 bfd_vma t0, t1, i0, i1, i2; local
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp597 NVPTX::SETP_f16x2rr, DL, MVT::i1, MVT::i1, N->getOperand(0),
817 case MVT::i1:
2203 // If we have an i1, use an 8-bit store. The lowering code in
2280 // If we have an i1, use an 8-bit store. The lowering code in
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp302 // Mips does not have i1 type, so use i32 for
312 // Load extented operations for i1 types must be promoted
314 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
315 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
316 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
342 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
413 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp751 // Combine low-overhead loop intrinsics so that we can lower i1 types.
1018 // ARM does not have i1 sign extending load.
1020 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1026 setIndexedLoadAction(im, MVT::i1, Legal);
1030 setIndexedStoreAction(im, MVT::i1, Legal);
1280 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1721 return MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());
3702 DAG.getSetCC(dl, MVT::i1, CLSHi, Constant31, ISD::CondCode::SETEQ);
3704 DAG.getSetCC(dl, MVT::i1, Hi, Constant0, ISD::CondCode::SETEQ);
6233 if (Op.getValueType().getVectorElementType() != MVT::i1)
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp4177 assert(Setcc.getSimpleValueType().getVectorElementType() == MVT::i1 &&
4304 MaskVT = MVT::getVectorVT(MVT::i1, NumElts);
4521 if (Node->getOperand(0).getValueType().getVectorElementType() == MVT::i1)
4545 if (NVT.isVector() && NVT.getVectorElementType() == MVT::i1) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp96 setLoadExtAction(N, XLenVT, MVT::i1, Promote);
114 for (auto VT : {MVT::i1, MVT::i8, MVT::i16})
/freebsd-11-stable/contrib/sqlite3/
H A Dsqlite3.c96780 int i1; local
108532 int i1 = sqlite3SchemaToIndex(db, sParse.pNewTrigger->pTabSchema); local
172256 sqlite3_int64 i1 = 0; /* Last position from pp1 */ local
172599 sqlite3_int64 i1 = 0; local
172700 sqlite3_int64 i1 = 0; local
222336 int i1 = p1 - pIter->aSeg; local
222418 int i1; /* Index of left-hand Fts5SegIter */ local
224705 int i1 = 0; local
225009 int i1 = i*nMerge; local
228411 int i1 = (iPhrase==0 ? 0 : pSorter->aIdx[iPhrase-1]); local
228751 int i1 = (iPhrase==0 ? 0 : pSorter->aIdx[iPhrase-1]); local
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/freebsd-11-stable/crypto/openssl/crypto/bn/asm/
H A Dsparcv8.S536 #define ap(I) [%i1+4*I]
H A Dsparcv8plus.S643 #define ap(I) [%i1+4*I]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp60 setLoadExtAction(N, VT, MVT::i1, Promote);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAGHVX.cpp1202 MVT BoolTy = MVT::getVectorVT(MVT::i1, 8*HwLen); // XXX
H A DHexagonInstrInfo.cpp710 unsigned Done = TII->createVR(MF, MVT::i1);
1988 if (VT == MVT::i1) {
3224 // e.g. jump_t t1 (i1)
3226 // Jumpers = {i2, i1}
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1022 .Case("i0", SP::I0).Case("i1", SP::I1).Case("i2", SP::I2).Case("i3", SP::I3)
1474 // Sparc doesn't have i1 sign extending load
1476 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1492 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
/freebsd-11-stable/contrib/gcc/
H A Dfold-const.c1814 tree i1 = TREE_IMAGPART (arg1);
1824 imag = const_binop (code, i1, i2, notrunc);
1830 const_binop (MULT_EXPR, i1, i2, notrunc),
1834 const_binop (MULT_EXPR, i1, r2, notrunc),
1848 const_binop (MULT_EXPR, i1, i2, notrunc),
1852 const_binop (MULT_EXPR, i1, r2, notrunc),
8742 /* Try replacing &a[i1] + c * i2 with &a[i1 + i2], if c is step
9127 /* Try replacing &a[i1] - c * i2 with &a[i1
1803 tree i1 = TREE_IMAGPART (arg1); local
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