Searched refs:Subtarget (Results 51 - 75 of 170) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp49 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
51 const X86Subtarget *Subtarget; member in class:__anon103::final
64 Subtarget = &funcInfo.MF->getSubtarget<X86Subtarget>();
65 X86ScalarSSEf64 = Subtarget->hasSSE2();
66 X86ScalarSSEf32 = Subtarget->hasSSE1();
141 return Subtarget->getInstrInfo();
321 bool HasSSE41 = Subtarget->hasSSE41();
322 bool HasAVX = Subtarget->hasAVX();
323 bool HasAVX2 = Subtarget->hasAVX2();
324 bool HasAVX512 = Subtarget
1339 X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) argument
3155 computeBytesPoppedByCalleeForSRet(const X86Subtarget *Subtarget, CallingConv::ID CC, ImmutableCallSite *CS) argument
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H A DX86AsmPrinter.h29 const X86Subtarget *Subtarget = nullptr; member in class:llvm::X86AsmPrinter
124 const X86Subtarget &getSubtarget() const { return *Subtarget; }
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCAsmPrinter.cpp83 const PPCSubtarget *Subtarget = nullptr; member in class:__anon99::PPCAsmPrinter
122 Subtarget = &MF.getSubtarget<PPCSubtarget>();
182 if (Subtarget->hasLazyResolverStub(GV)) {
211 if (!Subtarget->isDarwin())
309 if (!Subtarget->isDarwin())
419 int TOCSaveOffset = Subtarget->getFrameLowering()->getTOCSaveOffset();
428 if (!Subtarget->isELFv2ABI()) {
490 ((Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::X3) ||
491 (!Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::R3)) &&
494 ((Subtarget
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H A DPPCFrameLowering.h23 const PPCSubtarget &Subtarget; member in class:llvm::PPCFrameLowering
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp88 bool isMicroMips = Subtarget.inMicroMipsMode();
387 if (Subtarget.getABI().ArePtrs64bit()) {
405 bool isMicroMips = Subtarget.inMicroMipsMode();
578 MipsABIInfo ABI = Subtarget.getABI();
608 const MipsSubtarget &STI = Subtarget;
676 if (Subtarget.isGP64bit())
782 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
786 assert(!(Subtarget.isFP64bit() && !Subtarget
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H A DMipsTargetMachine.cpp123 Subtarget(nullptr),
132 Subtarget = &DefaultSubtarget;
213 Subtarget = &MF->getSubtarget<MipsSubtarget>();
284 if (Subtarget->allowMixed16_32()) {
H A DMipsCCState.cpp71 const MipsSubtarget &Subtarget) {
73 if (Subtarget.inMips16HardFloat()) {
70 getSpecialCallingConvForCallee(const SDNode *Callee, const MipsSubtarget &Subtarget) argument
H A DMipsTargetObjectFile.cpp97 const MipsSubtarget &Subtarget = local
101 if (!Subtarget.useSmallSection())
H A DMipsISelDAGToDAG.h34 : SelectionDAGISel(TM, OL), Subtarget(nullptr) {}
50 const MipsSubtarget *Subtarget; member in class:llvm::MipsDAGToDAGISel
H A DMipsSEISelDAGToDAG.cpp41 Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
42 if (Subtarget->inMips16Mode())
131 if (!Subtarget->isABI_O32()) { // N32, N64
171 if (!Subtarget->useOddSPReg()) {
178 if (Subtarget->isABI_FPXX() && !Subtarget->hasMTHC1())
513 if (!Subtarget->hasMSA())
526 MinSizeInBits, !Subtarget->isLittle()))
748 MVT VT = Subtarget->isGP64bit() ? MVT::i64 : MVT::i32;
757 ReplaceNode(Node, CurDAG->getMachineNode(Subtarget
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp109 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
111 const ARMSubtarget *Subtarget; member in class:__anon2150::final
126 Subtarget(
129 TM(funcInfo.MF->getTarget()), TII(*Subtarget->getInstrInfo()),
130 TLI(*Subtarget->getTargetLowering()) {
444 if (!Subtarget->hasVFP2Base()) return false;
471 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
483 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
500 if (Subtarget->useMovt())
542 if (Subtarget
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430TargetMachine.cpp50 Subtarget(TT, CPU, FS, *this) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiTargetMachine.cpp66 Subtarget(TT, Cpu, FeatureString, *this, Options, getCodeModel(),
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp84 const AArch64Subtarget &Subtarget = static_cast<const AArch64Subtarget &>( local
86 bool IsDarwinILP32 = Subtarget.isTargetILP32() && Subtarget.isTargetMachO();
149 unsigned SlotAlign = Subtarget.isTargetDarwin() ? 1 : 8;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCTargetMachine.cpp42 Subtarget(TT, CPU, FS, *this) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.h31 const VESubtarget *Subtarget; member in class:llvm::VETargetLowering
H A DVEFrameLowering.cpp178 const VESubtarget &Subtarget = MF.getSubtarget<VESubtarget>(); local
180 *static_cast<const VEInstrInfo *>(Subtarget.getInstrInfo());
182 *static_cast<const VERegisterInfo *>(Subtarget.getRegisterInfo());
220 NumBytes = Subtarget.getAdjustedFrameSize(NumBytes);
H A DVETargetMachine.cpp76 TLOF(createTLOF()), Subtarget(TT, CPU, FS, *this) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.h40 const SparcSubtarget& Subtarget; member in class:llvm::SparcInstrInfo
H A DSparcInstrInfo.cpp36 Subtarget(ST) {}
333 if (Subtarget.isV9()) {
343 if (Subtarget.isV9()) {
344 if (Subtarget.hasHardQuad()) {
484 Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
497 assert(Subtarget.isTargetLinux() &&
500 const int64_t Offset = Subtarget.is64Bit() ? 0x28 : 0x14;
501 MI.setDesc(get(Subtarget.is64Bit() ? SP::LDXri : SP::LDri));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp42 : TargetLowering(TM), Subtarget(&STI) {
43 auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32;
53 Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32);
59 if (Subtarget->hasSIMD128()) {
65 if (Subtarget->hasUnimplementedSIMD128()) {
70 computeRegisterProperties(Subtarget->getRegisterInfo());
118 if (Subtarget->hasSIMD128())
121 if (Subtarget->hasUnimplementedSIMD128())
126 if (Subtarget->hasSIMD128()) {
135 if (Subtarget
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H A DWebAssemblyMCInstLower.cpp74 const WebAssemblySubtarget &Subtarget = Printer.getSubtarget(); local
87 uint8_t(Subtarget.hasAddr64() ? wasm::WASM_TYPE_I64
111 Params.push_back(Subtarget.hasAddr64() ? wasm::ValType::I64
115 getLibcallSignature(Subtarget, Name, Returns, Params);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp84 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); local
85 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
197 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>(); local
201 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList
213 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); local
217 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/MIRParser/
H A DMIParser.h52 const TargetSubtargetInfo &Subtarget; member in struct:llvm::PerTargetMIParsingState
149 : Subtarget(STI) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp24 if (Subtarget.useHVX64BOps()) {
43 } else if (Subtarget.useHVX128BOps()) {
58 bool Use64b = Subtarget.useHVX64BOps();
276 return Subtarget.isHVXVectorType(Ty) &&
277 Ty.getSizeInBits() == 8 * Subtarget.getVectorLength();
282 return Subtarget.isHVXVectorType(Ty) &&
283 Ty.getSizeInBits() == 16 * Subtarget.getVectorLength();
357 unsigned HwLen = Subtarget.getVectorLength();
482 assert(4*Words.size() == Subtarget.getVectorLength());
505 unsigned HwLen = Subtarget
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