Searched refs:MBB (Results 101 - 125 of 513) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600FrameLowering.h24 MachineBasicBlock &MBB) const override {}
26 MachineBasicBlock &MBB) const override {}
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp32 void NVPTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB, argument
36 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
68 BuildMI(MBB, I, DL, get(Op), DestReg)
72 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
95 bool NVPTXInstrInfo::analyzeBranch(MachineBasicBlock &MBB, argument
101 MachineBasicBlock::iterator I = MBB.end();
102 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I))
109 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
127 if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
154 unsigned NVPTXInstrInfo::removeBranch(MachineBasicBlock &MBB, argument
180 insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DPHIElimination.cpp85 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
87 void LowerPHINode(MachineBasicBlock &MBB,
98 bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
103 bool isLiveIn(unsigned Reg, const MachineBasicBlock *MBB);
104 bool isLiveOutPastPHIs(unsigned Reg, const MachineBasicBlock *MBB);
160 for (auto &MBB : MF)
161 Changed |= SplitPHIEdges(MF, MBB, MLI);
168 for (auto &MBB : MF)
169 Changed |= EliminatePHINodes(MF, MBB);
205 MachineBasicBlock &MBB) {
204 EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) argument
240 LowerPHINode(MachineBasicBlock &MBB, MachineBasicBlock::iterator LastPHIIt) argument
562 SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB, MachineLoopInfo *MLI) argument
642 isLiveIn(unsigned Reg, const MachineBasicBlock *MBB) argument
651 isLiveOutPastPHIs(unsigned Reg, const MachineBasicBlock *MBB) argument
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H A DBranchFolding.h68 void setBlock(MachineBasicBlock *MBB) { argument
69 Block = MBB;
113 void setBlock(MachineBasicBlock *MBB) { argument
114 getMergePotentialsElt().setBlock(MBB);
142 BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const;
143 void setBlockFreq(const MachineBasicBlock *MBB, BlockFrequency F);
145 const MachineBasicBlock *MBB) const;
173 /// Given a machine basic block and an iterator into it, split the MBB so
175 /// iterator. This returns the new MBB.
185 /// MachineBasicBlock::iterator into that MBB indicatin
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp31 void BPFInstrInfo::copyPhysReg(MachineBasicBlock &MBB, argument
36 BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg)
39 BuildMI(MBB, I, DL, get(BPF::MOV_rr_32), DestReg)
124 void BPFInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, argument
130 if (I != MBB.end())
134 BuildMI(MBB, I, DL, get(BPF::STD))
139 BuildMI(MBB, I, DL, get(BPF::STW32))
147 void BPFInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, argument
153 if (I != MBB.end())
157 BuildMI(MBB,
164 analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
219 insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const argument
240 removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyExceptionInfo.h68 bool contains(const MachineBasicBlock *MBB) const {
69 return BlockSet.count(MBB);
72 void addBlock(MachineBasicBlock *MBB) { argument
73 Blocks.push_back(MBB);
74 BlockSet.insert(MBB);
125 WebAssemblyException *getOutermostException(MachineBasicBlock *MBB) const;
145 // Return the innermost exception that MBB lives in. If the block is not in an
147 WebAssemblyException *getExceptionFor(const MachineBasicBlock *MBB) const {
148 return BBMap.lookup(MBB);
151 void changeExceptionFor(MachineBasicBlock *MBB, WebAssemblyExceptio argument
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H A DWebAssemblyInstrInfo.cpp56 void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB, argument
62 auto &MRI = MBB.getParent()->getRegInfo();
84 BuildMI(MBB, I, DL, get(CopyOpcode), DestReg)
102 bool WebAssemblyInstrInfo::analyzeBranch(MachineBasicBlock &MBB, argument
107 const auto &MFI = *MBB.getParent()->getInfo<WebAssemblyFunctionInfo>();
115 for (MachineInstr &MI : MBB.terminators()) {
158 unsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB, argument
162 MachineBasicBlock::instr_iterator I = MBB.instr_end();
165 while (I != MBB.instr_begin()) {
173 I = MBB
180 insertBranch( MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const argument
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H A DWebAssemblyInstrInfo.h49 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
56 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
60 unsigned removeBranch(MachineBasicBlock &MBB,
62 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.h36 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
40 void storeRegToStackSlot(MachineBasicBlock &MBB,
46 void loadRegFromStackSlot(MachineBasicBlock &MBB,
52 void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
58 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
63 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
68 unsigned insertIndirectBranch(MachineBasicBlock &MBB,
73 unsigned removeBranch(MachineBasicBlock &MBB,
109 // Return true if MBB is safe to outline from, and return any target-specific
111 virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
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H A DRISCVFrameLowering.h29 void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
30 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
47 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
60 void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp44 static void generateStackAdjustment(MachineBasicBlock &MBB, argument
72 BuildMI(MBB, MBBI, dl, TII.get(AdjOp), StackPtr)
98 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
100 MachineFunction &MF = *MBB.getParent();
109 generateStackAdjustment(MBB, MBBI, *ST.getInstrInfo(), DebugLoc(),
117 MachineBasicBlock &MBB) const {
124 MachineBasicBlock::iterator MBBI = MBB.begin();
143 BuildMI(MBB, MBBI, dl, TII->get(Opc), ARC::SP)
149 BuildMI(MBB, MBBI, dl, TII->get(ARC::ST_AW_rs9))
160 BuildMI(MBB, MBB
97 adjustStackToMatchRecords( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, bool Allocate) const argument
402 spillCalleeSavedRegisters( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
420 restoreCalleeSavedRegisters( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
452 emitRegUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned Reg, int NumBytes, bool IsAdd, const ARCInstrInfo *TII) argument
469 eliminateCallFramePseudoInstr( MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument
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H A DARCInstrInfo.cpp145 /// Analyze the branching code at the end of MBB, returning
170 bool ARCInstrInfo::analyzeBranch(MachineBasicBlock &MBB, argument
176 MachineBasicBlock::iterator I = MBB.end();
177 if (I == MBB.begin())
189 if (I == MBB.begin())
232 while (DI != MBB.end()) {
243 if (I == MBB.begin())
254 unsigned ARCInstrInfo::removeBranch(MachineBasicBlock &MBB, argument
257 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
258 if (I == MBB
281 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &dl, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const argument
293 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
322 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
358 loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const argument
370 insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, const DebugLoc &dl, int *BytesAdded) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCExpandISEL.cpp60 // A map of MBB numbers to their lists of contained ISEL instructions.
62 // the ISEL from the MBB not from this list.
68 void handleSpecialCases(BlockISELList &BIL, MachineBasicBlock *MBB);
69 void reorganizeBlockLayout(BlockISELList &BIL, MachineBasicBlock *MBB);
158 for (MachineBasicBlock &MBB : *MF) {
160 for (MachineInstr &MI : MBB)
164 ISELInstructions.insert(std::make_pair(MBB.getNumber(), thisBlockISELs));
227 MachineBasicBlock *MBB = (*I)->getParent(); local
234 BuildMI(*MBB, (*I), dl, TII->get(isISEL8(**I) ? PPC::OR8 : PPC::OR))
263 MachineBasicBlock *MBB) {
262 handleSpecialCases(BlockISELList &BIL, MachineBasicBlock *MBB) argument
327 reorganizeBlockLayout(BlockISELList &BIL, MachineBasicBlock *MBB) argument
497 MachineBasicBlock *MBB = BIL.back()->getParent(); local
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H A DPPCTLSDynamicCall.cpp49 bool processBlock(MachineBasicBlock &MBB) { argument
52 bool Is64Bit = MBB.getParent()->getSubtarget<PPCSubtarget>().isPPC64();
54 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
113 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0)
117 MachineInstr *Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3)
126 MachineInstr *Call = (BuildMI(MBB, I, DL, TII->get(Opc2), GPR3)
131 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKUP)).addImm(0).addImm(0);
133 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), OutReg)
145 LIS->repairIntervalsInRange(&MBB, Firs
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp159 bool SparcInstrInfo::analyzeBranch(MachineBasicBlock &MBB, argument
164 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
165 if (I == MBB.end())
176 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
200 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
212 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))
242 unsigned SparcInstrInfo::insertBranch(MachineBasicBlock &MBB, argument
255 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
263 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
265 BuildMI(&MBB, D
273 removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const argument
305 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const argument
395 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
434 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineBlockFrequencyInfo.h1 //===- MachineBlockFrequencyInfo.h - MBB Frequency Analysis -----*- C++ -*-===//
62 BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const;
64 Optional<uint64_t> getBlockProfileCount(const MachineBasicBlock *MBB) const;
67 bool isIrrLoopHeader(const MachineBasicBlock *MBB);
80 const MachineBasicBlock *MBB) const;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.h38 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
41 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
45 void storeRegToStackSlot(MachineBasicBlock &MBB,
51 void loadRegFromStackSlot(MachineBasicBlock &MBB,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.cpp60 static void EmitDefCfaRegister(MachineBasicBlock &MBB, argument
66 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
70 static void EmitDefCfaOffset(MachineBasicBlock &MBB, argument
74 MachineFunction &MF = *MBB.getParent();
77 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
81 static void EmitCfiOffset(MachineBasicBlock &MBB, argument
85 MachineFunction &MF = *MBB.getParent();
88 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
98 static void IfNeededExtSP(MachineBasicBlock &MBB, argument
107 BuildMI(MBB, MBB
121 IfNeededLDAWSP(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &dl, const TargetInstrInfo &TII, int OffsetFromTop, int &RemainingAdj) argument
175 getFrameIndexMMO(MachineBasicBlock &MBB, int FrameIndex, MachineMemOperand::Flags flags) argument
190 RestoreSpillList(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &dl, const TargetInstrInfo &TII, int &RemainingAdj, SmallVectorImpl<StackSlotInfo> &SpillList) argument
416 spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
452 restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
486 eliminateCallFramePseudoInstr( MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument
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H A DXCoreFrameToArgsOffsetElim.cpp53 MachineBasicBlock &MBB = *MFI; local
54 for (MachineBasicBlock::iterator MBBI = MBB.begin(), EE = MBB.end();
59 MBBI = TII.loadImmediate(MBB, MBBI, Reg, StackSize);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.h27 void emitCalleeSavedFrameMoves(MachineBasicBlock &MBB,
31 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
36 void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
37 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
39 bool canUseAsPrologue(const MachineBasicBlock &MBB) const override;
50 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
55 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
H A DAArch64CompressJumpTables.cpp40 int computeBlockSize(MachineBasicBlock &MBB);
67 int AArch64CompressJumpTables::computeBlockSize(MachineBasicBlock &MBB) { argument
69 for (const MachineInstr &MI : MBB)
79 for (MachineBasicBlock &MBB : *MF) {
80 const Align Alignment = MBB.getAlignment();
86 BlockInfo[MBB.getNumber()] = AlignedOffset;
87 Offset = AlignedOffset + computeBlockSize(MBB);
156 for (MachineBasicBlock &MBB : *MF) {
157 int Offset = BlockInfo[MBB.getNumber()];
158 for (MachineInstr &MI : MBB) {
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H A DAArch64RedundantCopyElimination.cpp93 bool knownRegValInBlock(MachineInstr &CondBr, MachineBasicBlock *MBB,
96 bool optimizeBlock(MachineBasicBlock *MBB);
113 /// condition. To do so, this function checks to see if the basic block \p MBB
116 /// in \p MBB for some cases. Otherwise, we find and inspect the NZCV setting
121 /// the constant in \p MBB for some cases. If we find any constant values, push
125 MachineInstr &CondBr, MachineBasicBlock *MBB,
132 MBB == CondBr.getOperand(1).getMBB()) ||
134 MBB != CondBr.getOperand(1).getMBB())) {
150 if ((CC == AArch64CC::EQ && BrTarget != MBB) ||
151 (CC == AArch64CC::NE && BrTarget == MBB))
124 knownRegValInBlock( MachineInstr &CondBr, MachineBasicBlock *MBB, SmallVectorImpl<RegImm> &KnownRegs, MachineBasicBlock::iterator &FirstUse) argument
279 optimizeBlock(MachineBasicBlock *MBB) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.h74 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
77 void storeRegToStackSlot(MachineBasicBlock &MBB,
82 void loadRegFromStackSlot(MachineBasicBlock &MBB,
92 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
96 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
100 unsigned removeBranch(MachineBasicBlock &MBB,
110 unsigned insertIndirectBranch(MachineBasicBlock &MBB,
H A DAVRInstrInfo.cpp41 void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB, argument
45 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
52 BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg)
61 BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestLo)
63 BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestHi)
77 BuildMI(MBB, MI, DL, get(Opc), DestReg)
120 void AVRInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, argument
126 MachineFunction &MF = *MBB.getParent();
132 if (MI != MBB.end()) {
152 BuildMI(MBB, M
159 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
263 analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
398 insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const argument
437 removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const argument
558 insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp44 MachineBasicBlock &MBB);
51 MachineBasicBlock &MBB);
56 MachineBasicBlock &MBB);
71 MachineBasicBlock &MBB, bool OptIncDec);
76 MachineBasicBlock &MBB, bool OptIncDec,
88 MachineBasicBlock &MBB);
93 MachineInstr *postRAConvertToLEA(MachineBasicBlock &MBB,
126 FixupLEAPass::postRAConvertToLEA(MachineBasicBlock &MBB, argument
135 BuildMI(MBB, MBBI, MI.getDebugLoc(),
182 MachineFunction::iterator MFI = MBB
258 getPreviousInstr(MachineBasicBlock::iterator &I, MachineBasicBlock &MBB) argument
272 searchBackwards(MachineOperand &p, MachineBasicBlock::iterator &I, MachineBasicBlock &MBB) argument
352 optTwoAddrLEA(MachineBasicBlock::iterator &I, MachineBasicBlock &MBB, bool OptIncDec, bool UseLEAForSP) const argument
442 processInstruction(MachineBasicBlock::iterator &I, MachineBasicBlock &MBB) argument
461 seekLEAFixup(MachineOperand &p, MachineBasicBlock::iterator &I, MachineBasicBlock &MBB) argument
480 processInstructionForSlowLEA(MachineBasicBlock::iterator &I, MachineBasicBlock &MBB) argument
529 processInstrForSlow3OpLEA(MachineBasicBlock::iterator &I, MachineBasicBlock &MBB, bool OptIncDec) argument
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