1//===-- AVRInstrInfo.h - AVR Instruction Information ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the AVR implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_AVR_INSTR_INFO_H
14#define LLVM_AVR_INSTR_INFO_H
15
16#include "llvm/CodeGen/TargetInstrInfo.h"
17
18#include "AVRRegisterInfo.h"
19
20#define GET_INSTRINFO_HEADER
21#include "AVRGenInstrInfo.inc"
22#undef GET_INSTRINFO_HEADER
23
24namespace llvm {
25
26namespace AVRCC {
27
28/// AVR specific condition codes.
29/// These correspond to `AVR_*_COND` in `AVRInstrInfo.td`.
30/// They must be kept in synch.
31enum CondCodes {
32  COND_EQ, //!< Equal
33  COND_NE, //!< Not equal
34  COND_GE, //!< Greater than or equal
35  COND_LT, //!< Less than
36  COND_SH, //!< Unsigned same or higher
37  COND_LO, //!< Unsigned lower
38  COND_MI, //!< Minus
39  COND_PL, //!< Plus
40  COND_INVALID
41};
42
43} // end of namespace AVRCC
44
45namespace AVRII {
46
47/// Specifies a target operand flag.
48enum TOF {
49  MO_NO_FLAG,
50
51  /// On a symbol operand, this represents the lo part.
52  MO_LO = (1 << 1),
53
54  /// On a symbol operand, this represents the hi part.
55  MO_HI = (1 << 2),
56
57  /// On a symbol operand, this represents it has to be negated.
58  MO_NEG = (1 << 3)
59};
60
61} // end of namespace AVRII
62
63/// Utilities related to the AVR instruction set.
64class AVRInstrInfo : public AVRGenInstrInfo {
65public:
66  explicit AVRInstrInfo();
67
68  const AVRRegisterInfo &getRegisterInfo() const { return RI; }
69  const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
70  AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
71  AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const;
72  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
73
74  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
75                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
76                   bool KillSrc) const override;
77  void storeRegToStackSlot(MachineBasicBlock &MBB,
78                           MachineBasicBlock::iterator MI, unsigned SrcReg,
79                           bool isKill, int FrameIndex,
80                           const TargetRegisterClass *RC,
81                           const TargetRegisterInfo *TRI) const override;
82  void loadRegFromStackSlot(MachineBasicBlock &MBB,
83                            MachineBasicBlock::iterator MI, unsigned DestReg,
84                            int FrameIndex, const TargetRegisterClass *RC,
85                            const TargetRegisterInfo *TRI) const override;
86  unsigned isLoadFromStackSlot(const MachineInstr &MI,
87                               int &FrameIndex) const override;
88  unsigned isStoreToStackSlot(const MachineInstr &MI,
89                              int &FrameIndex) const override;
90
91  // Branch analysis.
92  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
93                     MachineBasicBlock *&FBB,
94                     SmallVectorImpl<MachineOperand> &Cond,
95                     bool AllowModify = false) const override;
96  unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
97                        MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
98                        const DebugLoc &DL,
99                        int *BytesAdded = nullptr) const override;
100  unsigned removeBranch(MachineBasicBlock &MBB,
101                        int *BytesRemoved = nullptr) const override;
102  bool
103  reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
104
105  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
106
107  bool isBranchOffsetInRange(unsigned BranchOpc,
108                             int64_t BrOffset) const override;
109
110  unsigned insertIndirectBranch(MachineBasicBlock &MBB,
111                                MachineBasicBlock &NewDestBB,
112                                const DebugLoc &DL,
113                                int64_t BrOffset,
114                                RegScavenger *RS) const override;
115private:
116  const AVRRegisterInfo RI;
117};
118
119} // end namespace llvm
120
121#endif // LLVM_AVR_INSTR_INFO_H
122