/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCTargetDesc.cpp | 257 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0); local 258 MAI->addInitialFrameState(Inst); 312 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 317 const auto &Desc = Info->get(Inst.getOpcode()); 318 for (unsigned i = 0, e = Inst.getNumOperands(); i != e; i++) { 320 int64_t Imm = Inst.getOperand(i).getImm() * 4;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcAsmPrinter.cpp | 129 MCInst Inst; local 130 Inst.setOpcode(Opcode); 131 Inst.addOperand(RD); 132 Inst.addOperand(RS1); 133 Inst.addOperand(Src2); 134 OutStreamer.EmitInstruction(Inst, STI);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstructionCombining.cpp | 1434 Instruction *InstCombiner::foldVectorBinop(BinaryOperator &Inst) { argument 1435 if (!Inst.getType()->isVectorTy()) return nullptr; 1437 BinaryOperator::BinaryOps Opcode = Inst.getOpcode(); 1438 unsigned NumElts = cast<VectorType>(Inst.getType())->getNumElements(); 1439 Value *LHS = Inst.getOperand(0), *RHS = Inst.getOperand(1); 1460 BO->copyIRFlags(&Inst); 1463 BO->copyIRFlags(&Inst); 1470 if (!isSafeToSpeculativelyExecute(&Inst)) 1476 BO->copyIRFlags(&Inst); 3448 Instruction *Inst = &*BBI++; local 3464 LLVM_DEBUG(dbgs() << "IC: ConstFold to: " << *C << " from: " << *Inst local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMELFStreamer.cpp | 99 void emitInst(uint32_t Inst, char Suffix = '\0') override; 254 void ARMTargetAsmStreamer::emitInst(uint32_t Inst, char Suffix) { 258 OS << "\t0x" << Twine::utohexstr(Inst) << "\n"; 410 void emitInst(uint32_t Inst, char Suffix = '\0') override; 489 void EmitInstruction(const MCInst &Inst, 496 MCELFStreamer::EmitInstruction(Inst, STI); 499 void emitInst(uint32_t Inst, char Suffix) { 512 Buffer[Size - II - 1] = uint8_t(Inst >> I * CHAR_BIT); 527 Buffer[Size - II - 2] = uint8_t(Inst >> I0 * CHAR_BIT); 528 Buffer[Size - II - 1] = uint8_t(Inst >> I [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIAnnotateControlFlow.cpp | 232 if (Instruction *Inst = dyn_cast<Instruction>(Cond)) { 233 BasicBlock *Parent = Inst->getParent(); 235 if (L->contains(Inst)) {
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H A D | AMDGPUTargetTransformInfo.cpp | 180 const Instruction *Inst = dyn_cast<Instruction>(Op); local 181 if (!Inst || L->isLoopInvariant(Op)) 184 if (llvm::any_of(L->getSubLoops(), [Inst](const Loop* SubLoop) { 185 return SubLoop->contains(Inst); })) 310 bool GCNTTIImpl::getTgtMemIntrinsic(IntrinsicInst *Inst, argument 312 switch (Inst->getIntrinsicID()) { 320 auto *Ordering = dyn_cast<ConstantInt>(Inst->getArgOperand(2)); 321 auto *Volatile = dyn_cast<ConstantInt>(Inst->getArgOperand(4)); 329 Info.PtrVal = Inst->getArgOperand(0);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetSchedule.cpp | 266 unsigned TargetSchedModel::computeInstrLatency(const MCInst &Inst) const { 268 return capLatency(SchedModel.computeInstrLatency(*STI, *TII, Inst)); 269 return computeInstrLatency(Inst.getOpcode());
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | DivergenceAnalysis.cpp | 138 const auto *Inst = dyn_cast<const Instruction>(&Val); local 139 if (!Inst) 143 for (const auto *Loop = LI.getLoopFor(Inst->getParent());
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H A D | AliasAnalysisEvaluator.cpp | 115 Instruction &Inst = *I; local 116 if (auto *Call = dyn_cast<CallBase>(&Inst)) { 128 for (Instruction::op_iterator OI = Inst.op_begin(), OE = Inst.op_end();
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | CSEInfo.cpp | 157 if (auto *Inst = getNodeIfExists(ID, MBB, InsertPos)) { 158 LLVM_DEBUG(dbgs() << "CSEInfo::Found Instr " << *Inst->MI;); 159 return const_cast<MachineInstr *>(Inst->MI);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
H A D | LowerExpectIntrinsic.cpp | 339 Instruction *Inst = &*BI++; local 340 CallInst *CI = dyn_cast<CallInst>(Inst); 342 if (SelectInst *SI = dyn_cast<SelectInst>(Inst)) {
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H A D | SCCP.cpp | 580 if (BBExecutable.count(I->getParent())) // Inst is executable? 1844 Instruction *Inst = &*BI++; local 1845 if (Inst->getType()->isVoidTy() || Inst->isTerminator()) 1848 if (tryToReplaceWithConstant(Solver, Inst)) { 1849 if (isInstructionTriviallyDead(Inst)) 1850 Inst->eraseFromParent(); 2096 Instruction *Inst = &*BI++; local 2097 if (Inst->getType()->isVoidTy()) 2099 if (tryToReplaceWithConstant(Solver, Inst)) { 2166 Instruction *Inst = &*BI++; local [all...] |
H A D | LoopIdiomRecognize.cpp | 583 Instruction *Inst = &*I++; local 585 if (MemSetInst *MSI = dyn_cast<MemSetInst>(Inst)) { 1285 Instruction *Inst = &*Iter; local 1286 if (Inst->getOpcode() != Instruction::Add) 1289 ConstantInt *Inc = dyn_cast<ConstantInt>(Inst->getOperand(1)); 1293 PHINode *Phi = getRecurrenceVar(Inst->getOperand(0), Inst, LoopEntry); 1299 for (User *U : Inst->users()) { 1307 CountInst = Inst; 1410 Instruction *Inst local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/FuzzMutate/ |
H A D | IRMutator.h | 102 void mutate(Instruction &Inst, RandomIRBuilder &IB) override;
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/ |
H A D | MCWinCOFFStreamer.h | 74 void EmitInstToData(const MCInst &Inst, const MCSubtargetInfo &STI) override;
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Analysis/ |
H A D | DivergenceAnalysis.h | 88 /// \brief Computes whether \p Inst is divergent based on the 91 /// \returns Whether \p Inst is divergent. 94 bool updateNormalInstruction(const Instruction &Inst) const;
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Transforms/ |
H A D | Instrumentation.h | 109 // Helper function that transforms Inst (either an indirect-call instruction, or 111 // if (Inst.CalledValue == F) 114 // Inst(...); 122 Instruction *promoteIndirectCall(Instruction *Inst, Function *F, uint64_t Count,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/ |
H A D | HWAddressSanitizer.cpp | 1098 for (auto &Inst : BB) { 1100 if (AllocaInst *AI = dyn_cast<AllocaInst>(&Inst)) { 1106 if (isa<ReturnInst>(Inst) || isa<ResumeInst>(Inst) || 1107 isa<CleanupReturnInst>(Inst)) 1108 RetVec.push_back(&Inst); 1110 if (auto *DDI = dyn_cast<DbgVariableIntrinsic>(&Inst)) 1115 if (InstrumentLandingPads && isa<LandingPadInst>(Inst)) 1116 LandingPadVec.push_back(&Inst); 1122 Value *Addr = isInterestingMemoryAccess(&Inst, [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Coroutines/ |
H A D | CoroInstr.h | 12 // if (auto *SF = dyn_cast<CoroSubFnInst>(Inst)) 132 // TODO: Add a check that any remaining users of Inst are after coro.begin 134 auto *Inst = cast<Instruction>(Arg); local 135 if (Inst->use_empty()) { 136 Inst->eraseFromParent(); 139 Inst->moveBefore(getCoroBegin()->getNextNode());
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/freebsd-11-stable/contrib/llvm-project/llvm/tools/bugpoint/ |
H A D | CrashDebugger.cpp | 788 Instruction *Inst = &*I++; local 789 if (!Instructions.count(Inst) && !Inst->isTerminator() && 790 !Inst->isEHPad() && !Inst->getType()->isTokenTy() && 791 !Inst->isSwiftError()) { 792 if (!Inst->getType()->isVoidTy()) 793 Inst->replaceAllUsesWith(UndefValue::get(Inst->getType())); 794 Inst [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCChecker.cpp | 55 MCInst const &Inst = *I.getInst(); local 56 if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) { 57 init(*Inst.getOperand(0).getInst()); 58 init(*Inst.getOperand(1).getInst()); 60 init(Inst); 495 MCInst const &Inst = *I.getInst(); local 496 unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs(); 498 MCOperand const &Operand = Inst.getOperand(j); 502 reportError(Inst.getLoc(), "Cannot write to read-only register `" +
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsTargetStreamer.cpp | 1205 MCInst Inst; local 1259 MCInst Inst; 1262 Inst.setOpcode(Mips::OR); 1263 Inst.addOperand(MCOperand::createReg(GPReg)); 1264 Inst.addOperand(MCOperand::createReg(SaveLocation)); 1265 Inst.addOperand(MCOperand::createReg(Mips::ZERO)); 1267 Inst.setOpcode(Mips::LD); 1268 Inst.addOperand(MCOperand::createReg(GPReg)); 1269 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1270 Inst [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEInstrInfo.cpp | 619 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin(); local 628 if (Inst->Opc == LUi) 629 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd)); 631 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg) 632 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 635 for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst) 636 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill) 637 .addImm(SignExtend64<16>(Inst [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Object/ |
H A D | RecordStreamer.cpp | 84 void RecordStreamer::EmitInstruction(const MCInst &Inst, argument 86 MCStreamer::EmitInstruction(Inst, STI);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCAsmBackend.cpp | 167 bool mayNeedRelaxation(const MCInst &Inst, 181 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
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