Searched refs:FP (Results 76 - 100 of 107) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/clang/lib/Frontend/
H A DCompilerInvocation.cpp868 CodeGenOptions::FramePointerKind FP; local
872 FP = CodeGenOptions::FramePointerKind::None;
874 FP = CodeGenOptions::FramePointerKind::NonLeaf;
876 FP = CodeGenOptions::FramePointerKind::All;
883 Opts.setFramePointer(FP);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DSplitKit.cpp469 ValueForcePair FP(Force ? nullptr : VNI, Force);
472 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), FP));
H A DMachineInstr.cpp543 if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
544 const FastMathFlags Flags = FP->getFastMathFlags();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DConstantFolding.cpp132 APFloat FP(DestTy->getFltSemantics(), Result);
133 return ConstantFP::get(DestTy->getContext(), FP);
171 // we have something in FP form, recast it as integer.
173 // Fold to an vector of integers with same size as our FP type.
184 // Okay, we know the destination is integer, if the input is FP, convert
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp1102 Register FP = local
1104 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), FP, VT);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp479 .addReg(AArch64::FP)
H A DAArch64InstrInfo.cpp3169 if ((DestReg == AArch64::FP && SrcReg == AArch64::SP) ||
3170 (SrcReg == AArch64::FP && DestReg == AArch64::SP)) {
3632 // FP Opcodes that can be combined with a FMUL
3901 assert(false && "Unsupported FP instruction in combiner\n");
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp420 // the combined constant into an FP reg.
1008 // load. Now we must move from the GRP to the FP register.
1566 unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg); local
1567 if (FP == 0) return false;
1577 TII.get(Opc), ResultReg).addReg(FP));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp3228 case Mips::SP: return Mips::FP;
3229 case Mips::FP: return Mips::RA;
5417 case Mips::F30: return Mips::FP;
5456 case Mips::COP030: return Mips::FP;
6634 } else if (!(((RegNo == Mips::FP || RegNo == Mips::RA ||
6643 ((RegNo != Mips::FP && RegNo != Mips::RA && !isGP64bit()) ||
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp261 // z10 has instructions for signed but not unsigned FP conversion.
2654 // be done directly. Mode is CmpMode::Int for integer comparisons, CmpMode::FP
2658 enum class CmpMode { Int, FP, StrictFP, SignalingFP };
2665 case CmpMode::FP: return SystemZISD::VFCMPE;
2675 case CmpMode::FP: return SystemZISD::VFCMPHE;
2685 case CmpMode::FP: return SystemZISD::VFCMPH;
2694 case CmpMode::FP: return 0;
2791 Chain ? CmpMode::StrictFP : IsFP ? CmpMode::FP : CmpMode::Int;
/freebsd-11-stable/contrib/llvm-project/clang/lib/Sema/
H A DSemaLookup.cpp817 if (const FunctionProtoType *FP =
820 for (unsigned IParm = 0, e = FP->getNumParams(); IParm != e; ++IParm) {
823 nullptr, FP->getParamType(IParm),
H A DSemaTemplateInstantiate.cpp2068 FunctionProtoTypeLoc FP = TL.castAs<FunctionProtoTypeLoc>();
2069 for (ParmVarDecl *P : FP.getParams()) {
H A DSemaCodeComplete.cpp5211 if (auto FP = T->getAs<FunctionProtoType>()) {
5212 if (!TooManyArguments(FP->getNumParams(), Args.size(),
5214 FP->isVariadic())
5215 Results.push_back(ResultCandidate(FP));
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Demangle/
H A DItaniumDemangle.h4829 Node *FP = getDerived().parseFunctionParam(); local
4830 if (FP == nullptr)
4832 return make<EnclosingExpr>("sizeof... (", FP, ")");
/freebsd-11-stable/sys/contrib/edk2/Include/Library/
H A DBaseLib.h162 UINT64 FP; member in struct:__anon6007
166 // FP regs
6645 /// Byte packed structure for an FP/SSE/SSE2 context.
/freebsd-11-stable/crypto/openssl/crypto/bn/asm/
H A Dsparcv9a-mont.pl32 # additional note, SPARC64 V implements FP Multiply-Add instruction,
84 $ap_h="%l2"; # to these four vectors as double-precision FP values.
94 # FP register naming chart
121 $ASI_FL16_P=0xD2; # magic ASI value to engage 16-bit FP load
163 wr %g0,$ASI_FL16_P,%asi ! setup %asi for 16-bit FP loads
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp132 // Default FP mode for the current function.
835 if (ConstantFPSDNode *FP = dyn_cast<ConstantFPSDNode>(N))
836 Imm = FP->getValueAPF().bitcastToAPInt().getZExtValue();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfDebug.cpp661 Register FP = TRI->getFrameRegister(*MF);
662 bool IsSPorFP = (RegLoc == SP) || (RegLoc == FP);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp1046 assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
1305 MSP430::FP, VT);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp2427 Mips::S6, Mips::S7, Mips::FP};
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp423 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp578 case PPC::FP:
863 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
1150 // Store FP into *R0.
1152 .addReg(FPReg, RegState::Kill) // Save FP.
1240 // Define CFA in terms of BP. Do this in preference to using FP/SP,
1242 // offset from FP/SP.
1256 // Describe where FP was saved, at a fixed offset from CFA.
1265 // Describe where FP was saved, at a fixed offset from CFA.
1299 // Change the definition of CFA from SP+offset to FP+offset, because SP
1577 // could happen to be R0. Use FP instea
[all...]
/freebsd-11-stable/sys/mips/mips/
H A Dfp.S2219 move a2, a1 # code = FP CSR
2228 move a2, a0 # code = FP instruction
3178 * a0 contains the FP instruction
3189 * a0 contains the FP instruction
3282 * a0 contains the FP instruction
/freebsd-11-stable/contrib/llvm-project/clang/lib/CodeGen/
H A DCGExprScalar.cpp387 /// EmitFloatToBoolConversion - Perform an FP to boolean conversion.
806 #define VISITCOMP(CODE, UI, SI, FP, SIG) \
809 llvm::FCmpInst::FP, SIG); }
1238 // Cast to FP using the intrinsic if the half type itself isn't supported.
1361 // Make sure we cast in a single step if from another FP type.
1402 assert(ResTy->isIntegerTy(16) && "Only half FP requires extra conversion");
2570 // Another special case: half FP increment should be done via float
2665 // Generate a unary FNeg for FP ops.
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1222 // Calculate its FP value.
1227 llvm_unreachable("FP immediate is not exact");
2272 .Case("fp", AArch64::FP)
2579 // Parse FP representation.
4711 // instruction for FP registers correctly in some rare circumstances. Convert

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