Searched refs:operands (Results 26 - 50 of 59) sorted by relevance

123

/freebsd-10.0-release/contrib/binutils/opcodes/
H A Dppc-dis.c237 /* Make two passes over the operands. First see if any of them
241 for (opindex = opcode->operands; *opindex != 0; opindex++)
251 if (opcode->operands[0] != 0)
256 /* Now extract and print the operands. */
260 for (opindex = opcode->operands; *opindex != 0; opindex++)
272 /* If all of the optional operands have the value zero,
H A Ds390-dis.c170 if (opcode->operands[0] != 0)
175 /* Extract the operands. */
177 for (opindex = opcode->operands; *opindex != 0; opindex++)
H A Dcr16-dis.c126 /* Retrieve the number of operands for the current assembled instruction. */
133 for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++)
737 a.type = getargtype (instruction->operands[i].op_type);
738 a.size = getbits (instruction->operands[i].op_type);
739 shift = instruction->operands[i].shift;
H A Di386-opc.h29 /* how many operands */
30 unsigned int operands; member in struct:__anon687
100 #define W 0x2 /* set if operands can be words or dwords
203 the suffix directly to check memory operands. */
/freebsd-10.0-release/contrib/gcc/config/ia64/
H A Dia64.c699 /* Return 1 if the operands of a move are ok. */
722 /* Return 1 if the operands are ok for a floating point load pair. */
1314 ia64_split_tmode_move (rtx operands[])
1326 if (GET_CODE (operands[1]) == MEM
1327 && reg_overlap_mentioned_p (operands[0], operands[1]))
1329 rtx base = XEXP (operands[1], 0);
1333 if (REGNO (base) == REGNO (operands[0]))
1340 if (GET_CODE (operands[0]) == REG && GET_CODE (operands[
1309 ia64_split_tmode_move(rtx operands[]) argument
1403 ia64_expand_movxf_movrf(enum machine_mode mode, rtx operands[]) argument
1713 ia64_expand_vecint_cmov(rtx operands[]) argument
1765 ia64_expand_vecint_minmax(enum rtx_code code, enum machine_mode mode, rtx operands[]) argument
1819 ia64_expand_widen_sum(rtx operands[3], bool unsignedp) argument
1873 ia64_expand_dot_prod_v8qi(rtx operands[4], bool unsignedp) argument
[all...]
/freebsd-10.0-release/contrib/binutils/gas/
H A Dsymbols.c1312 both operands are in the same section. Otherwise, both
1313 operands must be absolute. We already handled the case of
3027 char * operands[3]; /* Up to three operands. */
3030 operands[0] = operands[1] = operands[2] = NULL;
3034 /* Match known operators -> fill in opstr, arity, operands[] and fall
3057 operands[0] = symbol_relc_make_sym (exp->X_add_symbol);
3058 operands[
3022 char * operands[3]; /* Up to three operands. */ local
[all...]
/freebsd-10.0-release/tools/test/testfloat/
H A Dtestsoftfloat.c819 int8 operands, roundingPrecision, roundingMode, tininessMode; local
833 operands = 0;
959 operands = 1;
964 operands = 2;
969 operands = 0;
1000 if ( operands == 1 ) {
1015 else if ( operands == 2 ) {
/freebsd-10.0-release/contrib/binutils/gas/config/
H A Dtc-i386.c124 /* OPERANDS gives the number of given operands. */
125 unsigned int operands; member in struct:_i386_insn
128 of given register, displacement, memory operands and immediate
129 operands. */
140 /* Flags for operands. */
1372 for (i = 0; i < x->operands; i++)
1391 fprintf (stdout, " %d operands ", t->operands);
1400 for (i = 0; i < t->operands; i++)
1650 operands, henc
[all...]
H A Dtc-cr16.c801 on the operands. This hash table then provides a quick index to
1047 /* Parsing different types of operands
1285 /* Parse the various operands. Each operand is then analyzed to fillup
1289 parse_operands (ins * cr16_ins, char *operands) argument
1293 int allocated = 0; /* Indicates a new operands string was allocated.*/
1294 char *operand[MAX_OPERANDS];/* Separating the operands. */
1300 operandS = operandH = operandT = operands;
1313 as_bad (_("Illegal operands (whitespace): `%s'"), ins_parse);
1347 /* Verifying correct syntax of operands (all brackets should be closed). */
1387 operands
1390 parse_insn(ins *insn, char *operands) argument
[all...]
H A Dtc-ppc.c1293 /* The operands must not overlap the opcode or each other. */
1294 for (o = op->operands; *o; ++o)
1310 (int) (o - op->operands), op->name);
2213 /* PowerPC operands are just expressions. The only real issue is
2215 an optional operand separate the operands only with commas (in some
2217 have optional operands). Most instructions with optional operands
2219 take either all their operands or none. So, before we start seriously
2220 parsing the operands, we check to see if we have optional operands,
2783 char *operands[10]; local
[all...]
/freebsd-10.0-release/contrib/llvm/utils/TableGen/
H A DDAGISelMatcher.h963 /// operands in the root of the pattern. The rest are appended to this node.
968 const unsigned *operands, unsigned numops,
973 VTs(vts, vts+numvts), Operands(operands, operands+numops),
1018 const unsigned *operands, unsigned numops,
1022 : EmitNodeMatcherCommon(opcodeName, vts, numvts, operands, numops, hasChain,
1041 const unsigned *operands, unsigned numops,
1045 : EmitNodeMatcherCommon(opcodeName, vts, numvts, operands, numops, hasChain,
966 EmitNodeMatcherCommon(const std::string &opcodeName, const MVT::SimpleValueType *vts, unsigned numvts, const unsigned *operands, unsigned numops, bool hasChain, bool hasInGlue, bool hasOutGlue, bool hasmemrefs, int numfixedarityoperands, bool isMorphNodeTo) argument
1016 EmitNodeMatcher(const std::string &opcodeName, const MVT::SimpleValueType *vts, unsigned numvts, const unsigned *operands, unsigned numops, bool hasChain, bool hasInFlag, bool hasOutFlag, bool hasmemrefs, int numfixedarityoperands, unsigned firstresultslot) argument
1039 MorphNodeToMatcher(const std::string &opcodeName, const MVT::SimpleValueType *vts, unsigned numvts, const unsigned *operands, unsigned numops, bool hasChain, bool hasInFlag, bool hasOutFlag, bool hasmemrefs, int numfixedarityoperands, const PatternToMatch &pattern) argument
H A DX86DisassemblerTables.cpp460 .operands[OperandIndex].encoding);
463 .operands[OperandIndex].type);
502 .operands[OperandIndex].encoding);
505 .operands[OperandIndex].type);
H A DX86RecognizableInstr.cpp500 Spec->operands[operandIndex].encoding = ENCODING_DUP;
501 Spec->operands[operandIndex].type =
508 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
510 Spec->operands[operandIndex].type = typeFromString(typeName,
543 // operandMapping maps from operands in OperandList to their originals.
591 "Unexpected number of operands for RawFrm");
599 "Unexpected number of operands for AddRegFrm");
610 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
613 "Unexpected number of operands for MRMDestRegFrm");
632 "Unexpected number of operands fo
[all...]
H A DCodeGenDAGPatterns.h189 /// constraint to the nodes operands. This returns true if it makes a
212 /// getNumOperands - This is the number of operands required or -1 if
233 /// constraints for this node to the operands of the node. This returns
615 const std::vector<Record*> &operands,
617 : Pattern(TP), Results(results), Operands(operands),
/freebsd-10.0-release/contrib/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.c297 * address, and other relevant data sizes to report operands correctly.
1097 * up if we're using (say) XMM or 8-bit register operands. That gets fixed in
1497 * operands for that instruction, interpreting them as it goes.
1499 * @param insn - The instruction whose operands are to be read and interpreted.
1500 * @return - 0 if all operands could be read; nonzero otherwise.
1509 /* If non-zero vvvv specified, need to make sure one of the operands
1515 switch (x86OperandSets[insn->spec->operands][index].encoding) {
1522 if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index]))
1544 if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM3 &&
1547 if (x86OperandSets[insn->spec->operands][inde
[all...]
H A DX86Disassembler.cpp462 // Addresses in an MCInst are represented as five operands:
760 return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0],
766 /// operands to an MCInst.
786 if (insn.operands[index].encoding != ENCODING_NONE) {
787 if (translateOperand(mcInst, insn.operands[index], insn, Dis)) {
H A DX86DisassemblerDecoder.h24 uint16_t operands;
468 needed to find relocation entries for adding symbolic operands */
500 /* The ModR/M byte, which contains most register operands and some portion of
501 all memory operands */
505 /* The SIB byte, used for more complex 32- or 64-bit memory operands */
509 /* The displacement, used for memory operands */
543 const struct OperandSpecifier *operands; member in struct:InternalInstruction
/freebsd-10.0-release/contrib/gcc/
H A Drecog.c67 /* Nonzero means allow operands to be volatile.
115 /* Check that X is an insn-body for an `asm' with operands
116 and that the operands mentioned in it are legitimate. */
122 rtx *operands;
141 operands = alloca (noperands * sizeof (rtx));
144 decode_asm_operands (x, operands, NULL, constraints, NULL);
154 if (! asm_operand_ok (operands[i], c))
318 we also require that the operands meet the constraints for
477 operands look similar. */
502 /* Verify that operands ar
121 rtx *operands; local
1472 decode_asm_operands(rtx body, rtx *operands, rtx **operand_locs, const char **constraints, enum machine_mode *modes) argument
[all...]
H A Dfinal.c143 /* Nonzero while outputting an `asm' with operands.
148 /* Number of operands of this insn, for an `asm' with operands. */
2092 /* Detect `asm' construct with operands. */
2375 If successful, verify that the operands satisfy the
2798 /* Report inconsistency between the assembler template and the operands.
2894 operand vector, OPORDER is the order to write the operands, and NOPS
2895 is the number of operands to write. */
2898 output_asm_operand_names (rtx *operands, int *oporder, int nops)
2906 rtx op = operands[oporde
2884 output_asm_operand_names(rtx *operands, int *oporder, int nops) argument
2928 output_asm_insn(const char *template, rtx *operands) argument
[all...]
/freebsd-10.0-release/contrib/binutils/include/opcode/
H A Dcr16.h81 The argument types correspond to instructions operands
116 /* CR16 operand types:The operand types correspond to instructions operands.*/
180 /* The operands in binary and assembly are placed in reverse order.
196 general-purpose registers) as operands. */
206 /* Maximum operands per instruction. */
265 /* Operands (always last, so unreferenced operands are initialized). */
266 operand_desc operands[MAX_OPERANDS]; member in struct:__anon594
306 /* The argument data structure for storing args (operands). */
319 /* Structure to hold information about predefined operands. */
369 /* CR16 operands tabl
[all...]
H A Dia64.h63 /* register operands: */
79 /* memory operands: */
82 /* indirect operands: */
94 /* immediate operands: */
269 /* Number of output operands: */
273 operands are zeroes. */
279 match (and are presumably filled in by operands). */
283 operand table. They appear in the order which the operands must
285 enum ia64_opnd operands[5]; member in struct:ia64_opcode
325 /* The operands tabl
[all...]
/freebsd-10.0-release/contrib/llvm/lib/IR/
H A DInstructions.cpp60 /// areInvalidOperands - Return a string if the specified operands are invalid
138 /// growOperands - grow operands - This grows the operand list in response
235 /// growOperands - grow operands - This grows the operand list in response to a
779 assert(BI.getNumOperands() == 3 && "BR can have 1 or 3 operands!");
1079 assert(getOperand(0) && getOperand(1) && "Both operands must be non-null!");
1093 OperandTraits<StoreInst>::operands(this),
1106 OperandTraits<StoreInst>::operands(this),
1120 OperandTraits<StoreInst>::operands(this),
1134 OperandTraits<StoreInst>::operands(this),
1150 OperandTraits<StoreInst>::operands(thi
[all...]
/freebsd-10.0-release/contrib/gcc/config/mips/
H A Dmips.c192 operands 1 and above. */
196 value and the arguments are mapped to operands 0 and above. */
202 operands for the movt.ps or movf.ps instruction (in assembly order). */
208 CCV2 or CCV4. The function arguments are mapped to operands 1 and
580 /* The operands passed to the last cmpMM expander. */
3296 The comparison operands are saved away by cmp{si,di,sf,df}. */
3299 gen_conditional_branch (rtx *operands, enum rtx_code code)
3305 emit_jump_insn (gen_condjump (condition, operands[0]));
3333 of operands passed to the conditional move define_expand. */
3336 gen_conditional_move (rtx *operands)
3286 gen_conditional_branch(rtx *operands, enum rtx_code code) argument
3323 gen_conditional_move(rtx *operands) argument
3342 mips_gen_conditional_trap(rtx *operands) argument
9341 mips_output_conditional_branch(rtx insn, rtx *operands, const char *branch_if_true, const char *branch_if_false) argument
9422 mips_output_order_conditional_branch(rtx insn, rtx *operands, bool inverted_p) argument
9546 mips_output_division(const char *division, rtx *operands) argument
[all...]
/freebsd-10.0-release/contrib/gcc/config/s390/
H A Ds390.c511 /* Given a comparison code OP (EQ, NE, etc.) and the operands
1112 /* We don't need to split if operands are directly accessible. */
1197 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1201 rtx *operands)
1204 rtx dst = operands[0];
1205 rtx src1 = operands[1];
1206 rtx src2 = operands[2];
1210 if (!s390_logical_operator_ok_p (operands))
1218 /* Widen operands if required. */
1248 if (dst != operands[
1200 s390_expand_logical_operator(enum rtx_code code, enum machine_mode mode, rtx *operands) argument
1255 s390_logical_operator_ok_p(rtx *operands) argument
3356 emit_symbolic_move(rtx *operands) argument
[all...]
/freebsd-10.0-release/lib/libc/softfloat/
H A Dtimesoftfloat.c2484 int8 operands, roundingPrecision, roundingMode, tininessMode; local
2489 operands = 0;
2575 operands = 1;
2580 operands = 2;
2585 operands = 0;
2609 else if ( operands == 1 ) {
2619 else if ( operands == 2 ) {

Completed in 394 milliseconds

123