gas/config/tc-i386.c

124     /* OPERANDS gives the number of given operands.  */
125     unsigned int operands;
128        of given register, displacement, memory operands and immediate
129        operands.  */
140     /* Flags for operands.  */
1372   for (i = 0; i < x->operands; i++)
1391   fprintf (stdout, " %d operands ", t->operands);
1400   for (i = 0; i < t->operands; i++)
1650      operands, hence the code here is free to improperly handle opcodes that
1651      have no operands (for better performance and smaller code). */
1660        call path can make opcodes without operands get here */
1718   /* First parse an instruction mnemonic & call i386_operand for the operands.
1737       /* "extrq" and insertq" are the only two instructions whose operands
1738 	 have to be reversed even though they have two immediate operands.
1745      operands at hand.  */
1747   /* All intel opcodes have reversed operands except for "bound" and
1749      instructions with 2 immediate operands so that the immediate segment
1752       && i.operands > 1
1769      making sure the overlap of the given operands types is consistent
1834       if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
1837 	     operands with an opcode suffix which is coded in the same
1839 	     those operands and remove them afterwards.  */
1842 	  for (x = 0; x < i.operands; x++)
1849 	  i.operands = 0;
1857       assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1860       i.op[i.operands].imms = exp;
1861       i.types[i.operands++] = Imm8;
1867   /* For insns with operands there are more diddles to do to the opcode.  */
1868   if (i.operands)
2180 		  i.operands + 1);
2193 			    i.operands + 1);
2196 			    i.operands + 1);
2206 		      i.operands + 1);
2228 	  this_operand = i.operands++;
2229 	  if (i.operands > MAX_OPERANDS)
2231 	      as_bad (_("spurious operands; (%d operands/instruction max)"),
2299   switch (i.operands)
2302       swap_2_operands (1, i.operands - 2);
2305       swap_2_operands (0, i.operands - 1);
2336       for (op = i.operands; --op >= 0;)
2353   for (op = i.operands; --op >= 0;)
2449   for (op = i.operands; --op >= 0;)
2562       /* Must have right number of operands.  */
2563       if (i.operands != t->operands)
2575       /* In general, don't allow 64-bit operands in 32-bit mode.  */
2583 	      || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2588       /* Do not verify operands when there are none.  */
2589       else if (!t->operands)
2633       switch (t->operands)
2669 	      /* Try reversing direction of operands.  */
2696 	      switch (t->operands)
2705 	      switch (t->operands)
2720 		     register consistency between operands 2 and 3.  */
2747       as_bad (_("suffix or operands invalid for `%s'"),
2841 	 based on register operands.  */
2873 	      for (op = i.operands; --op >= 0;)
2951 			"no register operands; can't size instruction"));
3025 	  if (i.operands != 2
3046   for (op = i.operands; --op >= 0;)
3115   for (op = i.operands; --op >= 0;)
3169   for (op = i.operands; --op >= 0; )
3201   for (op = i.operands; --op >= 0;)
3339 	   assert (i.operands == 3
3356 	   i.operands--;
3363 	   i.tm.operands--;
3373 	   i.operands++;
3404 	      if (i.operands == 2)
3435 	 on one of their operands, the default segment is ds.  */
3462   /* i.reg_operands MUST be the number of real register operands;
3468       switch (i.operands)
3474 	  /* When there are 3 operands, one of them may be immediate,
3483 	  /* When there are 4 operands, the first two must be immediate
3484 	     operands. The source operand will be the 3rd one.  */
3497       /* One of the register operands will be encoded in the i.tm.reg
3530     {			/* If it's not 2 reg operands...  */
3536 	  for (op = 0; op < i.operands; op++)
3539 	  assert (op < i.operands);
3712 	  for (op = 0; op < i.operands; op++)
3717 	  assert (op < i.operands);
4143   for (n = 0; n < i.operands; n++)
4175 		  for (n1 = 0; n1 < i.operands; n1++)
4244   for (n = 0; n < i.operands; n++)
4279 	       * have operands that look like
4312 	       * the assembler we treat operands of this form as not being
4389 /* Parse operands of the form
4610       as_bad (_("at most %d immediate operands are allowed"),
4748       as_bad (_("at most %d displacement operands are allowed"),
4935       /* Memory operands of SVME insns are special in that they only allow
6541 /* Parse operands using Intel syntax. This implements a recursive descent
6547 	  high-level macro operands are missing.
6700     char *next_operand;		/* Resume point when splitting operands.  */
6812 		  /* Swap base and index in 16-bit memory operands like
6842       this_operand = i.operands++;
7388 		as_bad (_("Register scaling only allowed in memory operands"));
7459 	   when we're parsing offset operands), we may need to remove any
7551 			      "in memory operands"));