1//===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the X86 Disassembler Emitter.
11// It contains the implementation of a single recognizable instruction.
12// Documentation for the disassembler emitter in general can be found in
13//  X86DisasemblerEmitter.h.
14//
15//===----------------------------------------------------------------------===//
16
17#include "X86RecognizableInstr.h"
18#include "X86DisassemblerShared.h"
19#include "X86ModRMFilters.h"
20#include "llvm/Support/ErrorHandling.h"
21#include <string>
22
23using namespace llvm;
24
25#define MRM_MAPPING     \
26  MAP(C1, 33)           \
27  MAP(C2, 34)           \
28  MAP(C3, 35)           \
29  MAP(C4, 36)           \
30  MAP(C8, 37)           \
31  MAP(C9, 38)           \
32  MAP(CA, 39)           \
33  MAP(CB, 40)           \
34  MAP(E8, 41)           \
35  MAP(F0, 42)           \
36  MAP(F8, 45)           \
37  MAP(F9, 46)           \
38  MAP(D0, 47)           \
39  MAP(D1, 48)           \
40  MAP(D4, 49)           \
41  MAP(D5, 50)           \
42  MAP(D6, 51)           \
43  MAP(D8, 52)           \
44  MAP(D9, 53)           \
45  MAP(DA, 54)           \
46  MAP(DB, 55)           \
47  MAP(DC, 56)           \
48  MAP(DD, 57)           \
49  MAP(DE, 58)           \
50  MAP(DF, 59)
51
52// A clone of X86 since we can't depend on something that is generated.
53namespace X86Local {
54  enum {
55    Pseudo      = 0,
56    RawFrm      = 1,
57    AddRegFrm   = 2,
58    MRMDestReg  = 3,
59    MRMDestMem  = 4,
60    MRMSrcReg   = 5,
61    MRMSrcMem   = 6,
62    MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63    MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64    MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65    MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
66    MRMInitReg  = 32,
67    RawFrmImm8  = 43,
68    RawFrmImm16 = 44,
69#define MAP(from, to) MRM_##from = to,
70    MRM_MAPPING
71#undef MAP
72    lastMRM
73  };
74
75  enum {
76    TB  = 1,
77    REP = 2,
78    D8 = 3, D9 = 4, DA = 5, DB = 6,
79    DC = 7, DD = 8, DE = 9, DF = 10,
80    XD = 11,  XS = 12,
81    T8 = 13,  P_TA = 14,
82    A6 = 15,  A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19
83  };
84}
85
86// If rows are added to the opcode extension tables, then corresponding entries
87// must be added here.
88//
89// If the row corresponds to a single byte (i.e., 8f), then add an entry for
90// that byte to ONE_BYTE_EXTENSION_TABLES.
91//
92// If the row corresponds to two bytes where the first is 0f, add an entry for
93// the second byte to TWO_BYTE_EXTENSION_TABLES.
94//
95// If the row corresponds to some other set of bytes, you will need to modify
96// the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
97// to the X86 TD files, except in two cases: if the first two bytes of such a
98// new combination are 0f 38 or 0f 3a, you just have to add maps called
99// THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
100// switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
101// in RecognizableInstr::emitDecodePath().
102
103#define ONE_BYTE_EXTENSION_TABLES \
104  EXTENSION_TABLE(80)             \
105  EXTENSION_TABLE(81)             \
106  EXTENSION_TABLE(82)             \
107  EXTENSION_TABLE(83)             \
108  EXTENSION_TABLE(8f)             \
109  EXTENSION_TABLE(c0)             \
110  EXTENSION_TABLE(c1)             \
111  EXTENSION_TABLE(c6)             \
112  EXTENSION_TABLE(c7)             \
113  EXTENSION_TABLE(d0)             \
114  EXTENSION_TABLE(d1)             \
115  EXTENSION_TABLE(d2)             \
116  EXTENSION_TABLE(d3)             \
117  EXTENSION_TABLE(f6)             \
118  EXTENSION_TABLE(f7)             \
119  EXTENSION_TABLE(fe)             \
120  EXTENSION_TABLE(ff)
121
122#define TWO_BYTE_EXTENSION_TABLES \
123  EXTENSION_TABLE(00)             \
124  EXTENSION_TABLE(01)             \
125  EXTENSION_TABLE(0d)             \
126  EXTENSION_TABLE(18)             \
127  EXTENSION_TABLE(71)             \
128  EXTENSION_TABLE(72)             \
129  EXTENSION_TABLE(73)             \
130  EXTENSION_TABLE(ae)             \
131  EXTENSION_TABLE(ba)             \
132  EXTENSION_TABLE(c7)
133
134#define THREE_BYTE_38_EXTENSION_TABLES \
135  EXTENSION_TABLE(F3)
136
137using namespace X86Disassembler;
138
139/// needsModRMForDecode - Indicates whether a particular instruction requires a
140///   ModR/M byte for the instruction to be properly decoded.  For example, a
141///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
142///   0b11.
143///
144/// @param form - The form of the instruction.
145/// @return     - true if the form implies that a ModR/M byte is required, false
146///               otherwise.
147static bool needsModRMForDecode(uint8_t form) {
148  if (form == X86Local::MRMDestReg    ||
149     form == X86Local::MRMDestMem    ||
150     form == X86Local::MRMSrcReg     ||
151     form == X86Local::MRMSrcMem     ||
152     (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
153     (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
154    return true;
155  else
156    return false;
157}
158
159/// isRegFormat - Indicates whether a particular form requires the Mod field of
160///   the ModR/M byte to be 0b11.
161///
162/// @param form - The form of the instruction.
163/// @return     - true if the form implies that Mod must be 0b11, false
164///               otherwise.
165static bool isRegFormat(uint8_t form) {
166  if (form == X86Local::MRMDestReg ||
167     form == X86Local::MRMSrcReg  ||
168     (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
169    return true;
170  else
171    return false;
172}
173
174/// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
175///   Useful for switch statements and the like.
176///
177/// @param init - A reference to the BitsInit to be decoded.
178/// @return     - The field, with the first bit in the BitsInit as the lowest
179///               order bit.
180static uint8_t byteFromBitsInit(BitsInit &init) {
181  int width = init.getNumBits();
182
183  assert(width <= 8 && "Field is too large for uint8_t!");
184
185  int     index;
186  uint8_t mask = 0x01;
187
188  uint8_t ret = 0;
189
190  for (index = 0; index < width; index++) {
191    if (static_cast<BitInit*>(init.getBit(index))->getValue())
192      ret |= mask;
193
194    mask <<= 1;
195  }
196
197  return ret;
198}
199
200/// byteFromRec - Extract a value at most 8 bits in with from a Record given the
201///   name of the field.
202///
203/// @param rec  - The record from which to extract the value.
204/// @param name - The name of the field in the record.
205/// @return     - The field, as translated by byteFromBitsInit().
206static uint8_t byteFromRec(const Record* rec, const std::string &name) {
207  BitsInit* bits = rec->getValueAsBitsInit(name);
208  return byteFromBitsInit(*bits);
209}
210
211RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
212                                     const CodeGenInstruction &insn,
213                                     InstrUID uid) {
214  UID = uid;
215
216  Rec = insn.TheDef;
217  Name = Rec->getName();
218  Spec = &tables.specForUID(UID);
219
220  if (!Rec->isSubClassOf("X86Inst")) {
221    ShouldBeEmitted = false;
222    return;
223  }
224
225  Prefix   = byteFromRec(Rec, "Prefix");
226  Opcode   = byteFromRec(Rec, "Opcode");
227  Form     = byteFromRec(Rec, "FormBits");
228  SegOvr   = byteFromRec(Rec, "SegOvrBits");
229
230  HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
231  HasAdSizePrefix  = Rec->getValueAsBit("hasAdSizePrefix");
232  HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
233  HasVEXPrefix     = Rec->getValueAsBit("hasVEXPrefix");
234  HasVEX_4VPrefix  = Rec->getValueAsBit("hasVEX_4VPrefix");
235  HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
236  HasVEX_WPrefix   = Rec->getValueAsBit("hasVEX_WPrefix");
237  HasMemOp4Prefix  = Rec->getValueAsBit("hasMemOp4Prefix");
238  IgnoresVEX_L     = Rec->getValueAsBit("ignoresVEX_L");
239  HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
240  IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
241
242  Name      = Rec->getName();
243  AsmString = Rec->getValueAsString("AsmString");
244
245  Operands = &insn.Operands.OperandList;
246
247  IsSSE            = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
248                     (Name.find("CRC32") != Name.npos);
249  HasFROperands    = hasFROperands();
250  HasVEX_LPrefix   = Rec->getValueAsBit("hasVEX_L");
251
252  // Check for 64-bit inst which does not require REX
253  Is32Bit = false;
254  Is64Bit = false;
255  // FIXME: Is there some better way to check for In64BitMode?
256  std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
257  for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
258    if (Predicates[i]->getName().find("32Bit") != Name.npos) {
259      Is32Bit = true;
260      break;
261    }
262    if (Predicates[i]->getName().find("64Bit") != Name.npos) {
263      Is64Bit = true;
264      break;
265    }
266  }
267  // FIXME: These instructions aren't marked as 64-bit in any way
268  Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
269             Rec->getName() == "MASKMOVDQU64" ||
270             Rec->getName() == "POPFS64" ||
271             Rec->getName() == "POPGS64" ||
272             Rec->getName() == "PUSHFS64" ||
273             Rec->getName() == "PUSHGS64" ||
274             Rec->getName() == "REX64_PREFIX" ||
275             Rec->getName().find("MOV64") != Name.npos ||
276             Rec->getName().find("PUSH64") != Name.npos ||
277             Rec->getName().find("POP64") != Name.npos;
278
279  ShouldBeEmitted  = true;
280}
281
282void RecognizableInstr::processInstr(DisassemblerTables &tables,
283                                     const CodeGenInstruction &insn,
284                                     InstrUID uid)
285{
286  // Ignore "asm parser only" instructions.
287  if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
288    return;
289
290  RecognizableInstr recogInstr(tables, insn, uid);
291
292  recogInstr.emitInstructionSpecifier(tables);
293
294  if (recogInstr.shouldBeEmitted())
295    recogInstr.emitDecodePath(tables);
296}
297
298InstructionContext RecognizableInstr::insnContext() const {
299  InstructionContext insnContext;
300
301  if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
302    if (HasVEX_LPrefix && HasVEX_WPrefix) {
303      if (HasOpSizePrefix)
304        insnContext = IC_VEX_L_W_OPSIZE;
305      else
306        llvm_unreachable("Don't support VEX.L and VEX.W together");
307    } else if (HasOpSizePrefix && HasVEX_LPrefix)
308      insnContext = IC_VEX_L_OPSIZE;
309    else if (HasOpSizePrefix && HasVEX_WPrefix)
310      insnContext = IC_VEX_W_OPSIZE;
311    else if (HasOpSizePrefix)
312      insnContext = IC_VEX_OPSIZE;
313    else if (HasVEX_LPrefix &&
314             (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
315      insnContext = IC_VEX_L_XS;
316    else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
317                                Prefix == X86Local::T8XD ||
318                                Prefix == X86Local::TAXD))
319      insnContext = IC_VEX_L_XD;
320    else if (HasVEX_WPrefix &&
321             (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
322      insnContext = IC_VEX_W_XS;
323    else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
324                                Prefix == X86Local::T8XD ||
325                                Prefix == X86Local::TAXD))
326      insnContext = IC_VEX_W_XD;
327    else if (HasVEX_WPrefix)
328      insnContext = IC_VEX_W;
329    else if (HasVEX_LPrefix)
330      insnContext = IC_VEX_L;
331    else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
332             Prefix == X86Local::TAXD)
333      insnContext = IC_VEX_XD;
334    else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
335      insnContext = IC_VEX_XS;
336    else
337      insnContext = IC_VEX;
338  } else if (Is64Bit || HasREX_WPrefix) {
339    if (HasREX_WPrefix && HasOpSizePrefix)
340      insnContext = IC_64BIT_REXW_OPSIZE;
341    else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
342                                 Prefix == X86Local::T8XD ||
343                                 Prefix == X86Local::TAXD))
344      insnContext = IC_64BIT_XD_OPSIZE;
345    else if (HasOpSizePrefix &&
346             (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
347      insnContext = IC_64BIT_XS_OPSIZE;
348    else if (HasOpSizePrefix)
349      insnContext = IC_64BIT_OPSIZE;
350    else if (HasAdSizePrefix)
351      insnContext = IC_64BIT_ADSIZE;
352    else if (HasREX_WPrefix &&
353             (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
354      insnContext = IC_64BIT_REXW_XS;
355    else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
356                                Prefix == X86Local::T8XD ||
357                                Prefix == X86Local::TAXD))
358      insnContext = IC_64BIT_REXW_XD;
359    else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
360             Prefix == X86Local::TAXD)
361      insnContext = IC_64BIT_XD;
362    else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
363      insnContext = IC_64BIT_XS;
364    else if (HasREX_WPrefix)
365      insnContext = IC_64BIT_REXW;
366    else
367      insnContext = IC_64BIT;
368  } else {
369    if (HasOpSizePrefix && (Prefix == X86Local::XD ||
370                            Prefix == X86Local::T8XD ||
371                            Prefix == X86Local::TAXD))
372      insnContext = IC_XD_OPSIZE;
373    else if (HasOpSizePrefix &&
374             (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
375      insnContext = IC_XS_OPSIZE;
376    else if (HasOpSizePrefix)
377      insnContext = IC_OPSIZE;
378    else if (HasAdSizePrefix)
379      insnContext = IC_ADSIZE;
380    else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
381             Prefix == X86Local::TAXD)
382      insnContext = IC_XD;
383    else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
384             Prefix == X86Local::REP)
385      insnContext = IC_XS;
386    else
387      insnContext = IC;
388  }
389
390  return insnContext;
391}
392
393RecognizableInstr::filter_ret RecognizableInstr::filter() const {
394  ///////////////////
395  // FILTER_STRONG
396  //
397
398  // Filter out intrinsics
399
400  assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
401
402  if (Form == X86Local::Pseudo ||
403      (IsCodeGenOnly && Name.find("_REV") == Name.npos))
404    return FILTER_STRONG;
405
406
407  // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
408  // printed as a separate "instruction".
409
410  if (Name.find("_Int") != Name.npos       ||
411      Name.find("Int_") != Name.npos)
412    return FILTER_STRONG;
413
414  // Filter out instructions with segment override prefixes.
415  // They're too messy to handle now and we'll special case them if needed.
416
417  if (SegOvr)
418    return FILTER_STRONG;
419
420
421  /////////////////
422  // FILTER_WEAK
423  //
424
425
426  // Filter out instructions with a LOCK prefix;
427  //   prefer forms that do not have the prefix
428  if (HasLockPrefix)
429    return FILTER_WEAK;
430
431  // Filter out alternate forms of AVX instructions
432  if (Name.find("_alt") != Name.npos ||
433      Name.find("XrYr") != Name.npos ||
434      (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
435      Name.find("_64mr") != Name.npos ||
436      Name.find("Xrr") != Name.npos ||
437      Name.find("rr64") != Name.npos)
438    return FILTER_WEAK;
439
440  // Special cases.
441
442  if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
443    return FILTER_WEAK;
444  if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
445    return FILTER_WEAK;
446
447  if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
448    return FILTER_WEAK;
449  if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
450    return FILTER_WEAK;
451  if (Name.find("Fs") != Name.npos)
452    return FILTER_WEAK;
453  if (Name == "PUSH64i16"         ||
454      Name == "MOVPQI2QImr"       ||
455      Name == "VMOVPQI2QImr"      ||
456      Name == "MMX_MOVD64rrv164"  ||
457      Name == "MOV64ri64i32"      ||
458      Name == "VMASKMOVDQU64"     ||
459      Name == "VEXTRACTPSrr64"    ||
460      Name == "VMOVQd64rr"        ||
461      Name == "VMOVQs64rr")
462    return FILTER_WEAK;
463
464  if (HasFROperands && Name.find("MOV") != Name.npos &&
465     ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
466      (Name.find("to") != Name.npos)))
467    return FILTER_STRONG;
468
469  return FILTER_NORMAL;
470}
471
472bool RecognizableInstr::hasFROperands() const {
473  const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
474  unsigned numOperands = OperandList.size();
475
476  for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
477    const std::string &recName = OperandList[operandIndex].Rec->getName();
478
479    if (recName.find("FR") != recName.npos)
480      return true;
481  }
482  return false;
483}
484
485void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
486                                      unsigned &physicalOperandIndex,
487                                      unsigned &numPhysicalOperands,
488                                      const unsigned *operandMapping,
489                                      OperandEncoding (*encodingFromString)
490                                        (const std::string&,
491                                         bool hasOpSizePrefix)) {
492  if (optional) {
493    if (physicalOperandIndex >= numPhysicalOperands)
494      return;
495  } else {
496    assert(physicalOperandIndex < numPhysicalOperands);
497  }
498
499  while (operandMapping[operandIndex] != operandIndex) {
500    Spec->operands[operandIndex].encoding = ENCODING_DUP;
501    Spec->operands[operandIndex].type =
502      (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
503    ++operandIndex;
504  }
505
506  const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
507
508  Spec->operands[operandIndex].encoding = encodingFromString(typeName,
509                                                              HasOpSizePrefix);
510  Spec->operands[operandIndex].type = typeFromString(typeName,
511                                                     IsSSE,
512                                                     HasREX_WPrefix,
513                                                     HasOpSizePrefix);
514
515  ++operandIndex;
516  ++physicalOperandIndex;
517}
518
519void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
520  Spec->name       = Name;
521
522  if (!ShouldBeEmitted)
523    return;
524
525  switch (filter()) {
526  case FILTER_WEAK:
527    Spec->filtered = true;
528    break;
529  case FILTER_STRONG:
530    ShouldBeEmitted = false;
531    return;
532  case FILTER_NORMAL:
533    break;
534  }
535
536  Spec->insnContext = insnContext();
537
538  const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
539
540  unsigned numOperands = OperandList.size();
541  unsigned numPhysicalOperands = 0;
542
543  // operandMapping maps from operands in OperandList to their originals.
544  // If operandMapping[i] != i, then the entry is a duplicate.
545  unsigned operandMapping[X86_MAX_OPERANDS];
546  assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
547
548  for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
549    if (OperandList[operandIndex].Constraints.size()) {
550      const CGIOperandList::ConstraintInfo &Constraint =
551        OperandList[operandIndex].Constraints[0];
552      if (Constraint.isTied()) {
553        operandMapping[operandIndex] = operandIndex;
554        operandMapping[Constraint.getTiedOperand()] = operandIndex;
555      } else {
556        ++numPhysicalOperands;
557        operandMapping[operandIndex] = operandIndex;
558      }
559    } else {
560      ++numPhysicalOperands;
561      operandMapping[operandIndex] = operandIndex;
562    }
563  }
564
565#define HANDLE_OPERAND(class)               \
566  handleOperand(false,                      \
567                operandIndex,               \
568                physicalOperandIndex,       \
569                numPhysicalOperands,        \
570                operandMapping,             \
571                class##EncodingFromString);
572
573#define HANDLE_OPTIONAL(class)              \
574  handleOperand(true,                       \
575                operandIndex,               \
576                physicalOperandIndex,       \
577                numPhysicalOperands,        \
578                operandMapping,             \
579                class##EncodingFromString);
580
581  // operandIndex should always be < numOperands
582  unsigned operandIndex = 0;
583  // physicalOperandIndex should always be < numPhysicalOperands
584  unsigned physicalOperandIndex = 0;
585
586  switch (Form) {
587  case X86Local::RawFrm:
588    // Operand 1 (optional) is an address or immediate.
589    // Operand 2 (optional) is an immediate.
590    assert(numPhysicalOperands <= 2 &&
591           "Unexpected number of operands for RawFrm");
592    HANDLE_OPTIONAL(relocation)
593    HANDLE_OPTIONAL(immediate)
594    break;
595  case X86Local::AddRegFrm:
596    // Operand 1 is added to the opcode.
597    // Operand 2 (optional) is an address.
598    assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
599           "Unexpected number of operands for AddRegFrm");
600    HANDLE_OPERAND(opcodeModifier)
601    HANDLE_OPTIONAL(relocation)
602    break;
603  case X86Local::MRMDestReg:
604    // Operand 1 is a register operand in the R/M field.
605    // Operand 2 is a register operand in the Reg/Opcode field.
606    // - In AVX, there is a register operand in the VEX.vvvv field here -
607    // Operand 3 (optional) is an immediate.
608    if (HasVEX_4VPrefix)
609      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
610             "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
611    else
612      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
613             "Unexpected number of operands for MRMDestRegFrm");
614
615    HANDLE_OPERAND(rmRegister)
616
617    if (HasVEX_4VPrefix)
618      // FIXME: In AVX, the register below becomes the one encoded
619      // in ModRMVEX and the one above the one in the VEX.VVVV field
620      HANDLE_OPERAND(vvvvRegister)
621
622    HANDLE_OPERAND(roRegister)
623    HANDLE_OPTIONAL(immediate)
624    break;
625  case X86Local::MRMDestMem:
626    // Operand 1 is a memory operand (possibly SIB-extended)
627    // Operand 2 is a register operand in the Reg/Opcode field.
628    // - In AVX, there is a register operand in the VEX.vvvv field here -
629    // Operand 3 (optional) is an immediate.
630    if (HasVEX_4VPrefix)
631      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
632             "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
633    else
634      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
635             "Unexpected number of operands for MRMDestMemFrm");
636    HANDLE_OPERAND(memory)
637
638    if (HasVEX_4VPrefix)
639      // FIXME: In AVX, the register below becomes the one encoded
640      // in ModRMVEX and the one above the one in the VEX.VVVV field
641      HANDLE_OPERAND(vvvvRegister)
642
643    HANDLE_OPERAND(roRegister)
644    HANDLE_OPTIONAL(immediate)
645    break;
646  case X86Local::MRMSrcReg:
647    // Operand 1 is a register operand in the Reg/Opcode field.
648    // Operand 2 is a register operand in the R/M field.
649    // - In AVX, there is a register operand in the VEX.vvvv field here -
650    // Operand 3 (optional) is an immediate.
651    // Operand 4 (optional) is an immediate.
652
653    if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
654      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
655             "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
656    else
657      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
658             "Unexpected number of operands for MRMSrcRegFrm");
659
660    HANDLE_OPERAND(roRegister)
661
662    if (HasVEX_4VPrefix)
663      // FIXME: In AVX, the register below becomes the one encoded
664      // in ModRMVEX and the one above the one in the VEX.VVVV field
665      HANDLE_OPERAND(vvvvRegister)
666
667    if (HasMemOp4Prefix)
668      HANDLE_OPERAND(immediate)
669
670    HANDLE_OPERAND(rmRegister)
671
672    if (HasVEX_4VOp3Prefix)
673      HANDLE_OPERAND(vvvvRegister)
674
675    if (!HasMemOp4Prefix)
676      HANDLE_OPTIONAL(immediate)
677    HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
678    HANDLE_OPTIONAL(immediate)
679    break;
680  case X86Local::MRMSrcMem:
681    // Operand 1 is a register operand in the Reg/Opcode field.
682    // Operand 2 is a memory operand (possibly SIB-extended)
683    // - In AVX, there is a register operand in the VEX.vvvv field here -
684    // Operand 3 (optional) is an immediate.
685
686    if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
687      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
688             "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
689    else
690      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
691             "Unexpected number of operands for MRMSrcMemFrm");
692
693    HANDLE_OPERAND(roRegister)
694
695    if (HasVEX_4VPrefix)
696      // FIXME: In AVX, the register below becomes the one encoded
697      // in ModRMVEX and the one above the one in the VEX.VVVV field
698      HANDLE_OPERAND(vvvvRegister)
699
700    if (HasMemOp4Prefix)
701      HANDLE_OPERAND(immediate)
702
703    HANDLE_OPERAND(memory)
704
705    if (HasVEX_4VOp3Prefix)
706      HANDLE_OPERAND(vvvvRegister)
707
708    if (!HasMemOp4Prefix)
709      HANDLE_OPTIONAL(immediate)
710    HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
711    break;
712  case X86Local::MRM0r:
713  case X86Local::MRM1r:
714  case X86Local::MRM2r:
715  case X86Local::MRM3r:
716  case X86Local::MRM4r:
717  case X86Local::MRM5r:
718  case X86Local::MRM6r:
719  case X86Local::MRM7r:
720    // Operand 1 is a register operand in the R/M field.
721    // Operand 2 (optional) is an immediate or relocation.
722    // Operand 3 (optional) is an immediate.
723    if (HasVEX_4VPrefix)
724      assert(numPhysicalOperands <= 3 &&
725             "Unexpected number of operands for MRMnRFrm with VEX_4V");
726    else
727      assert(numPhysicalOperands <= 3 &&
728             "Unexpected number of operands for MRMnRFrm");
729    if (HasVEX_4VPrefix)
730      HANDLE_OPERAND(vvvvRegister)
731    HANDLE_OPTIONAL(rmRegister)
732    HANDLE_OPTIONAL(relocation)
733    HANDLE_OPTIONAL(immediate)
734    break;
735  case X86Local::MRM0m:
736  case X86Local::MRM1m:
737  case X86Local::MRM2m:
738  case X86Local::MRM3m:
739  case X86Local::MRM4m:
740  case X86Local::MRM5m:
741  case X86Local::MRM6m:
742  case X86Local::MRM7m:
743    // Operand 1 is a memory operand (possibly SIB-extended)
744    // Operand 2 (optional) is an immediate or relocation.
745    if (HasVEX_4VPrefix)
746      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
747             "Unexpected number of operands for MRMnMFrm");
748    else
749      assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
750             "Unexpected number of operands for MRMnMFrm");
751    if (HasVEX_4VPrefix)
752      HANDLE_OPERAND(vvvvRegister)
753    HANDLE_OPERAND(memory)
754    HANDLE_OPTIONAL(relocation)
755    break;
756  case X86Local::RawFrmImm8:
757    // operand 1 is a 16-bit immediate
758    // operand 2 is an 8-bit immediate
759    assert(numPhysicalOperands == 2 &&
760           "Unexpected number of operands for X86Local::RawFrmImm8");
761    HANDLE_OPERAND(immediate)
762    HANDLE_OPERAND(immediate)
763    break;
764  case X86Local::RawFrmImm16:
765    // operand 1 is a 16-bit immediate
766    // operand 2 is a 16-bit immediate
767    HANDLE_OPERAND(immediate)
768    HANDLE_OPERAND(immediate)
769    break;
770  case X86Local::MRM_F8:
771    if (Opcode == 0xc6) {
772      assert(numPhysicalOperands == 1 &&
773             "Unexpected number of operands for X86Local::MRM_F8");
774      HANDLE_OPERAND(immediate)
775    } else if (Opcode == 0xc7) {
776      assert(numPhysicalOperands == 1 &&
777             "Unexpected number of operands for X86Local::MRM_F8");
778      HANDLE_OPERAND(relocation)
779    }
780    break;
781  case X86Local::MRMInitReg:
782    // Ignored.
783    break;
784  }
785
786  #undef HANDLE_OPERAND
787  #undef HANDLE_OPTIONAL
788}
789
790void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
791  // Special cases where the LLVM tables are not complete
792
793#define MAP(from, to)                     \
794  case X86Local::MRM_##from:              \
795    filter = new ExactFilter(0x##from);   \
796    break;
797
798  OpcodeType    opcodeType  = (OpcodeType)-1;
799
800  ModRMFilter*  filter      = NULL;
801  uint8_t       opcodeToSet = 0;
802
803  switch (Prefix) {
804  // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
805  case X86Local::XD:
806  case X86Local::XS:
807  case X86Local::TB:
808    opcodeType = TWOBYTE;
809
810    switch (Opcode) {
811    default:
812      if (needsModRMForDecode(Form))
813        filter = new ModFilter(isRegFormat(Form));
814      else
815        filter = new DumbFilter();
816      break;
817#define EXTENSION_TABLE(n) case 0x##n:
818    TWO_BYTE_EXTENSION_TABLES
819#undef EXTENSION_TABLE
820      switch (Form) {
821      default:
822        llvm_unreachable("Unhandled two-byte extended opcode");
823      case X86Local::MRM0r:
824      case X86Local::MRM1r:
825      case X86Local::MRM2r:
826      case X86Local::MRM3r:
827      case X86Local::MRM4r:
828      case X86Local::MRM5r:
829      case X86Local::MRM6r:
830      case X86Local::MRM7r:
831        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
832        break;
833      case X86Local::MRM0m:
834      case X86Local::MRM1m:
835      case X86Local::MRM2m:
836      case X86Local::MRM3m:
837      case X86Local::MRM4m:
838      case X86Local::MRM5m:
839      case X86Local::MRM6m:
840      case X86Local::MRM7m:
841        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
842        break;
843      MRM_MAPPING
844      } // switch (Form)
845      break;
846    } // switch (Opcode)
847    opcodeToSet = Opcode;
848    break;
849  case X86Local::T8:
850  case X86Local::T8XD:
851  case X86Local::T8XS:
852    opcodeType = THREEBYTE_38;
853    switch (Opcode) {
854    default:
855      if (needsModRMForDecode(Form))
856        filter = new ModFilter(isRegFormat(Form));
857      else
858        filter = new DumbFilter();
859      break;
860#define EXTENSION_TABLE(n) case 0x##n:
861    THREE_BYTE_38_EXTENSION_TABLES
862#undef EXTENSION_TABLE
863      switch (Form) {
864      default:
865        llvm_unreachable("Unhandled two-byte extended opcode");
866      case X86Local::MRM0r:
867      case X86Local::MRM1r:
868      case X86Local::MRM2r:
869      case X86Local::MRM3r:
870      case X86Local::MRM4r:
871      case X86Local::MRM5r:
872      case X86Local::MRM6r:
873      case X86Local::MRM7r:
874        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
875        break;
876      case X86Local::MRM0m:
877      case X86Local::MRM1m:
878      case X86Local::MRM2m:
879      case X86Local::MRM3m:
880      case X86Local::MRM4m:
881      case X86Local::MRM5m:
882      case X86Local::MRM6m:
883      case X86Local::MRM7m:
884        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
885        break;
886      MRM_MAPPING
887      } // switch (Form)
888      break;
889    } // switch (Opcode)
890    opcodeToSet = Opcode;
891    break;
892  case X86Local::P_TA:
893  case X86Local::TAXD:
894    opcodeType = THREEBYTE_3A;
895    if (needsModRMForDecode(Form))
896      filter = new ModFilter(isRegFormat(Form));
897    else
898      filter = new DumbFilter();
899    opcodeToSet = Opcode;
900    break;
901  case X86Local::A6:
902    opcodeType = THREEBYTE_A6;
903    if (needsModRMForDecode(Form))
904      filter = new ModFilter(isRegFormat(Form));
905    else
906      filter = new DumbFilter();
907    opcodeToSet = Opcode;
908    break;
909  case X86Local::A7:
910    opcodeType = THREEBYTE_A7;
911    if (needsModRMForDecode(Form))
912      filter = new ModFilter(isRegFormat(Form));
913    else
914      filter = new DumbFilter();
915    opcodeToSet = Opcode;
916    break;
917  case X86Local::D8:
918  case X86Local::D9:
919  case X86Local::DA:
920  case X86Local::DB:
921  case X86Local::DC:
922  case X86Local::DD:
923  case X86Local::DE:
924  case X86Local::DF:
925    assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
926    opcodeType = ONEBYTE;
927    if (Form == X86Local::AddRegFrm) {
928      Spec->modifierType = MODIFIER_MODRM;
929      Spec->modifierBase = Opcode;
930      filter = new AddRegEscapeFilter(Opcode);
931    } else {
932      filter = new EscapeFilter(true, Opcode);
933    }
934    opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
935    break;
936  case X86Local::REP:
937  default:
938    opcodeType = ONEBYTE;
939    switch (Opcode) {
940#define EXTENSION_TABLE(n) case 0x##n:
941    ONE_BYTE_EXTENSION_TABLES
942#undef EXTENSION_TABLE
943      switch (Form) {
944      default:
945        llvm_unreachable("Fell through the cracks of a single-byte "
946                         "extended opcode");
947      case X86Local::MRM0r:
948      case X86Local::MRM1r:
949      case X86Local::MRM2r:
950      case X86Local::MRM3r:
951      case X86Local::MRM4r:
952      case X86Local::MRM5r:
953      case X86Local::MRM6r:
954      case X86Local::MRM7r:
955        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
956        break;
957      case X86Local::MRM0m:
958      case X86Local::MRM1m:
959      case X86Local::MRM2m:
960      case X86Local::MRM3m:
961      case X86Local::MRM4m:
962      case X86Local::MRM5m:
963      case X86Local::MRM6m:
964      case X86Local::MRM7m:
965        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
966        break;
967      MRM_MAPPING
968      } // switch (Form)
969      break;
970    case 0xd8:
971    case 0xd9:
972    case 0xda:
973    case 0xdb:
974    case 0xdc:
975    case 0xdd:
976    case 0xde:
977    case 0xdf:
978      filter = new EscapeFilter(false, Form - X86Local::MRM0m);
979      break;
980    default:
981      if (needsModRMForDecode(Form))
982        filter = new ModFilter(isRegFormat(Form));
983      else
984        filter = new DumbFilter();
985      break;
986    } // switch (Opcode)
987    opcodeToSet = Opcode;
988  } // switch (Prefix)
989
990  assert(opcodeType != (OpcodeType)-1 &&
991         "Opcode type not set");
992  assert(filter && "Filter not set");
993
994  if (Form == X86Local::AddRegFrm) {
995    if(Spec->modifierType != MODIFIER_MODRM) {
996      assert(opcodeToSet < 0xf9 &&
997             "Not enough room for all ADDREG_FRM operands");
998
999      uint8_t currentOpcode;
1000
1001      for (currentOpcode = opcodeToSet;
1002           currentOpcode < opcodeToSet + 8;
1003           ++currentOpcode)
1004        tables.setTableFields(opcodeType,
1005                              insnContext(),
1006                              currentOpcode,
1007                              *filter,
1008                              UID, Is32Bit, IgnoresVEX_L);
1009
1010      Spec->modifierType = MODIFIER_OPCODE;
1011      Spec->modifierBase = opcodeToSet;
1012    } else {
1013      // modifierBase was set where MODIFIER_MODRM was set
1014      tables.setTableFields(opcodeType,
1015                            insnContext(),
1016                            opcodeToSet,
1017                            *filter,
1018                            UID, Is32Bit, IgnoresVEX_L);
1019    }
1020  } else {
1021    tables.setTableFields(opcodeType,
1022                          insnContext(),
1023                          opcodeToSet,
1024                          *filter,
1025                          UID, Is32Bit, IgnoresVEX_L);
1026
1027    Spec->modifierType = MODIFIER_NONE;
1028    Spec->modifierBase = opcodeToSet;
1029  }
1030
1031  delete filter;
1032
1033#undef MAP
1034}
1035
1036#define TYPE(str, type) if (s == str) return type;
1037OperandType RecognizableInstr::typeFromString(const std::string &s,
1038                                              bool isSSE,
1039                                              bool hasREX_WPrefix,
1040                                              bool hasOpSizePrefix) {
1041  if (isSSE) {
1042    // For SSE instructions, we ignore the OpSize prefix and force operand
1043    // sizes.
1044    TYPE("GR16",              TYPE_R16)
1045    TYPE("GR32",              TYPE_R32)
1046    TYPE("GR64",              TYPE_R64)
1047  }
1048  if(hasREX_WPrefix) {
1049    // For instructions with a REX_W prefix, a declared 32-bit register encoding
1050    // is special.
1051    TYPE("GR32",              TYPE_R32)
1052  }
1053  if(!hasOpSizePrefix) {
1054    // For instructions without an OpSize prefix, a declared 16-bit register or
1055    // immediate encoding is special.
1056    TYPE("GR16",              TYPE_R16)
1057    TYPE("i16imm",            TYPE_IMM16)
1058  }
1059  TYPE("i16mem",              TYPE_Mv)
1060  TYPE("i16imm",              TYPE_IMMv)
1061  TYPE("i16i8imm",            TYPE_IMMv)
1062  TYPE("GR16",                TYPE_Rv)
1063  TYPE("i32mem",              TYPE_Mv)
1064  TYPE("i32imm",              TYPE_IMMv)
1065  TYPE("i32i8imm",            TYPE_IMM32)
1066  TYPE("u32u8imm",            TYPE_IMM32)
1067  TYPE("GR32",                TYPE_Rv)
1068  TYPE("i64mem",              TYPE_Mv)
1069  TYPE("i64i32imm",           TYPE_IMM64)
1070  TYPE("i64i8imm",            TYPE_IMM64)
1071  TYPE("GR64",                TYPE_R64)
1072  TYPE("i8mem",               TYPE_M8)
1073  TYPE("i8imm",               TYPE_IMM8)
1074  TYPE("GR8",                 TYPE_R8)
1075  TYPE("VR128",               TYPE_XMM128)
1076  TYPE("f128mem",             TYPE_M128)
1077  TYPE("f256mem",             TYPE_M256)
1078  TYPE("FR64",                TYPE_XMM64)
1079  TYPE("f64mem",              TYPE_M64FP)
1080  TYPE("sdmem",               TYPE_M64FP)
1081  TYPE("FR32",                TYPE_XMM32)
1082  TYPE("f32mem",              TYPE_M32FP)
1083  TYPE("ssmem",               TYPE_M32FP)
1084  TYPE("RST",                 TYPE_ST)
1085  TYPE("i128mem",             TYPE_M128)
1086  TYPE("i256mem",             TYPE_M256)
1087  TYPE("i64i32imm_pcrel",     TYPE_REL64)
1088  TYPE("i16imm_pcrel",        TYPE_REL16)
1089  TYPE("i32imm_pcrel",        TYPE_REL32)
1090  TYPE("SSECC",               TYPE_IMM3)
1091  TYPE("AVXCC",               TYPE_IMM5)
1092  TYPE("brtarget",            TYPE_RELv)
1093  TYPE("uncondbrtarget",      TYPE_RELv)
1094  TYPE("brtarget8",           TYPE_REL8)
1095  TYPE("f80mem",              TYPE_M80FP)
1096  TYPE("lea32mem",            TYPE_LEA)
1097  TYPE("lea64_32mem",         TYPE_LEA)
1098  TYPE("lea64mem",            TYPE_LEA)
1099  TYPE("VR64",                TYPE_MM64)
1100  TYPE("i64imm",              TYPE_IMMv)
1101  TYPE("opaque32mem",         TYPE_M1616)
1102  TYPE("opaque48mem",         TYPE_M1632)
1103  TYPE("opaque80mem",         TYPE_M1664)
1104  TYPE("opaque512mem",        TYPE_M512)
1105  TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
1106  TYPE("DEBUG_REG",           TYPE_DEBUGREG)
1107  TYPE("CONTROL_REG",         TYPE_CONTROLREG)
1108  TYPE("offset8",             TYPE_MOFFS8)
1109  TYPE("offset16",            TYPE_MOFFS16)
1110  TYPE("offset32",            TYPE_MOFFS32)
1111  TYPE("offset64",            TYPE_MOFFS64)
1112  TYPE("VR256",               TYPE_XMM256)
1113  TYPE("GR16_NOAX",           TYPE_Rv)
1114  TYPE("GR32_NOAX",           TYPE_Rv)
1115  TYPE("GR64_NOAX",           TYPE_R64)
1116  TYPE("vx32mem",             TYPE_M32)
1117  TYPE("vy32mem",             TYPE_M32)
1118  TYPE("vx64mem",             TYPE_M64)
1119  TYPE("vy64mem",             TYPE_M64)
1120  errs() << "Unhandled type string " << s << "\n";
1121  llvm_unreachable("Unhandled type string");
1122}
1123#undef TYPE
1124
1125#define ENCODING(str, encoding) if (s == str) return encoding;
1126OperandEncoding RecognizableInstr::immediateEncodingFromString
1127  (const std::string &s,
1128   bool hasOpSizePrefix) {
1129  if(!hasOpSizePrefix) {
1130    // For instructions without an OpSize prefix, a declared 16-bit register or
1131    // immediate encoding is special.
1132    ENCODING("i16imm",        ENCODING_IW)
1133  }
1134  ENCODING("i32i8imm",        ENCODING_IB)
1135  ENCODING("u32u8imm",        ENCODING_IB)
1136  ENCODING("SSECC",           ENCODING_IB)
1137  ENCODING("AVXCC",           ENCODING_IB)
1138  ENCODING("i16imm",          ENCODING_Iv)
1139  ENCODING("i16i8imm",        ENCODING_IB)
1140  ENCODING("i32imm",          ENCODING_Iv)
1141  ENCODING("i64i32imm",       ENCODING_ID)
1142  ENCODING("i64i8imm",        ENCODING_IB)
1143  ENCODING("i8imm",           ENCODING_IB)
1144  // This is not a typo.  Instructions like BLENDVPD put
1145  // register IDs in 8-bit immediates nowadays.
1146  ENCODING("VR256",           ENCODING_IB)
1147  ENCODING("VR128",           ENCODING_IB)
1148  ENCODING("FR32",            ENCODING_IB)
1149  ENCODING("FR64",            ENCODING_IB)
1150  errs() << "Unhandled immediate encoding " << s << "\n";
1151  llvm_unreachable("Unhandled immediate encoding");
1152}
1153
1154OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1155  (const std::string &s,
1156   bool hasOpSizePrefix) {
1157  ENCODING("GR16",            ENCODING_RM)
1158  ENCODING("GR32",            ENCODING_RM)
1159  ENCODING("GR64",            ENCODING_RM)
1160  ENCODING("GR8",             ENCODING_RM)
1161  ENCODING("VR128",           ENCODING_RM)
1162  ENCODING("FR64",            ENCODING_RM)
1163  ENCODING("FR32",            ENCODING_RM)
1164  ENCODING("VR64",            ENCODING_RM)
1165  ENCODING("VR256",           ENCODING_RM)
1166  errs() << "Unhandled R/M register encoding " << s << "\n";
1167  llvm_unreachable("Unhandled R/M register encoding");
1168}
1169
1170OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1171  (const std::string &s,
1172   bool hasOpSizePrefix) {
1173  ENCODING("GR16",            ENCODING_REG)
1174  ENCODING("GR32",            ENCODING_REG)
1175  ENCODING("GR64",            ENCODING_REG)
1176  ENCODING("GR8",             ENCODING_REG)
1177  ENCODING("VR128",           ENCODING_REG)
1178  ENCODING("FR64",            ENCODING_REG)
1179  ENCODING("FR32",            ENCODING_REG)
1180  ENCODING("VR64",            ENCODING_REG)
1181  ENCODING("SEGMENT_REG",     ENCODING_REG)
1182  ENCODING("DEBUG_REG",       ENCODING_REG)
1183  ENCODING("CONTROL_REG",     ENCODING_REG)
1184  ENCODING("VR256",           ENCODING_REG)
1185  errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1186  llvm_unreachable("Unhandled reg/opcode register encoding");
1187}
1188
1189OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1190  (const std::string &s,
1191   bool hasOpSizePrefix) {
1192  ENCODING("GR32",            ENCODING_VVVV)
1193  ENCODING("GR64",            ENCODING_VVVV)
1194  ENCODING("FR32",            ENCODING_VVVV)
1195  ENCODING("FR64",            ENCODING_VVVV)
1196  ENCODING("VR128",           ENCODING_VVVV)
1197  ENCODING("VR256",           ENCODING_VVVV)
1198  errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1199  llvm_unreachable("Unhandled VEX.vvvv register encoding");
1200}
1201
1202OperandEncoding RecognizableInstr::memoryEncodingFromString
1203  (const std::string &s,
1204   bool hasOpSizePrefix) {
1205  ENCODING("i16mem",          ENCODING_RM)
1206  ENCODING("i32mem",          ENCODING_RM)
1207  ENCODING("i64mem",          ENCODING_RM)
1208  ENCODING("i8mem",           ENCODING_RM)
1209  ENCODING("ssmem",           ENCODING_RM)
1210  ENCODING("sdmem",           ENCODING_RM)
1211  ENCODING("f128mem",         ENCODING_RM)
1212  ENCODING("f256mem",         ENCODING_RM)
1213  ENCODING("f64mem",          ENCODING_RM)
1214  ENCODING("f32mem",          ENCODING_RM)
1215  ENCODING("i128mem",         ENCODING_RM)
1216  ENCODING("i256mem",         ENCODING_RM)
1217  ENCODING("f80mem",          ENCODING_RM)
1218  ENCODING("lea32mem",        ENCODING_RM)
1219  ENCODING("lea64_32mem",     ENCODING_RM)
1220  ENCODING("lea64mem",        ENCODING_RM)
1221  ENCODING("opaque32mem",     ENCODING_RM)
1222  ENCODING("opaque48mem",     ENCODING_RM)
1223  ENCODING("opaque80mem",     ENCODING_RM)
1224  ENCODING("opaque512mem",    ENCODING_RM)
1225  ENCODING("vx32mem",         ENCODING_RM)
1226  ENCODING("vy32mem",         ENCODING_RM)
1227  ENCODING("vx64mem",         ENCODING_RM)
1228  ENCODING("vy64mem",         ENCODING_RM)
1229  errs() << "Unhandled memory encoding " << s << "\n";
1230  llvm_unreachable("Unhandled memory encoding");
1231}
1232
1233OperandEncoding RecognizableInstr::relocationEncodingFromString
1234  (const std::string &s,
1235   bool hasOpSizePrefix) {
1236  if(!hasOpSizePrefix) {
1237    // For instructions without an OpSize prefix, a declared 16-bit register or
1238    // immediate encoding is special.
1239    ENCODING("i16imm",        ENCODING_IW)
1240  }
1241  ENCODING("i16imm",          ENCODING_Iv)
1242  ENCODING("i16i8imm",        ENCODING_IB)
1243  ENCODING("i32imm",          ENCODING_Iv)
1244  ENCODING("i32i8imm",        ENCODING_IB)
1245  ENCODING("i64i32imm",       ENCODING_ID)
1246  ENCODING("i64i8imm",        ENCODING_IB)
1247  ENCODING("i8imm",           ENCODING_IB)
1248  ENCODING("i64i32imm_pcrel", ENCODING_ID)
1249  ENCODING("i16imm_pcrel",    ENCODING_IW)
1250  ENCODING("i32imm_pcrel",    ENCODING_ID)
1251  ENCODING("brtarget",        ENCODING_Iv)
1252  ENCODING("brtarget8",       ENCODING_IB)
1253  ENCODING("i64imm",          ENCODING_IO)
1254  ENCODING("offset8",         ENCODING_Ia)
1255  ENCODING("offset16",        ENCODING_Ia)
1256  ENCODING("offset32",        ENCODING_Ia)
1257  ENCODING("offset64",        ENCODING_Ia)
1258  errs() << "Unhandled relocation encoding " << s << "\n";
1259  llvm_unreachable("Unhandled relocation encoding");
1260}
1261
1262OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1263  (const std::string &s,
1264   bool hasOpSizePrefix) {
1265  ENCODING("RST",             ENCODING_I)
1266  ENCODING("GR32",            ENCODING_Rv)
1267  ENCODING("GR64",            ENCODING_RO)
1268  ENCODING("GR16",            ENCODING_Rv)
1269  ENCODING("GR8",             ENCODING_RB)
1270  ENCODING("GR16_NOAX",       ENCODING_Rv)
1271  ENCODING("GR32_NOAX",       ENCODING_Rv)
1272  ENCODING("GR64_NOAX",       ENCODING_RO)
1273  errs() << "Unhandled opcode modifier encoding " << s << "\n";
1274  llvm_unreachable("Unhandled opcode modifier encoding");
1275}
1276#undef ENCODING
1277