Searched refs:channel (Results 276 - 300 of 359) sorted by relevance

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/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/media/video/
H A Dw9966.c903 if(vch.channel != 0) // We only support one channel (#0)
923 if(vch.channel != 0)
H A Dzr36067.c3394 ("%s: ioctl VIDIOCGCHAN for channel %d\n",
3395 zr->name, v.channel));
3396 switch (v.channel) {
3411 "%s: VIDIOCGCHAN on not existing channel %d\n",
3412 zr->name, v.channel));
3449 || v.channel != zr->params.input) {
3462 ("%s: ioctl VIDIOCSCHAN: channel=%d, norm=%d\n",
3463 zr->name, v.channel, v.norm));
3464 switch (v.channel) {
3482 "%s: VIDIOCSCHAN on not existing channel
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H A Dbw-qcam.c729 if(v.channel!=0)
H A Dc-qcam.c539 if(v.channel!=0)
/asus-wl-520gu-7.0.1.45/src/router/library/libupnp-1.2.1/upnp/sample/tvctrlpt/
H A Dupnp_tv_ctrlpt.c443 int channel )
447 channel );
/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/char/
H A Dspecialix.c577 unsigned char channel; local
580 channel = sx_in(bp, CD186x_GICR) >> GICR_CHAN_OFF;
581 if (channel < CD186x_NCH) {
582 port = &sx_port[board_No(bp) * SX_NPORT + channel];
588 board_No(bp), what, channel);
1157 /* Setting up CD186x channel registers */
H A Drocket_int.h84 /* AIOP ID numbers, identifies AIOP type implementing channel */
85 #define AIOPID_NULL -1 /* no AIOP or channel exists */
92 #define NULLCHAN -1 /* identifies non-existant channel */
106 Channel Register Offsets for 1st channel in AIOP - Direct Access
225 #define RESETUART 0x20 /* reset channel's UART */
226 #define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */
227 #define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */
261 #define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */
333 CHANNEL_T *ChP; Ptr to channel structure
345 CHANNEL_T *ChP; Ptr to channel structur
1071 CHANNEL_t channel; member in struct:r_port
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/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/isdn/hisax/
H A Disar.c1360 if (bcs->channel)
1389 bcs->channel = bc;
1648 modeisar(bcs, 0, bcs->channel);
1695 bcs->channel = st->l1.bc;
1716 bcs = cs->channel[ic->arg].bcs;
H A Dl3dss1.c3 * EURO/DSS1 D-channel protocol
5 * German 1TR6 D-channel protocol
1236 u_char channel = 0; local
1294 channel = 0x08;
1296 channel |= 0x80;
1299 channel |= 0x01;
1301 channel |= 0x02;
1318 if (channel) {
1321 *p++ = channel;
2710 l3_debug(pc->st, "Restart for channel
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/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/sound/
H A Dad1848.c447 if (devc->mix_devices[i][j].nbits == 0) /* Inexistent channel */
527 static void ad1848_mixer_set_channel(ad1848_info *devc, int dev, int value, int channel) argument
532 regoffs = devc->mix_devices[dev][channel].regno;
533 muteregoffs = devc->mix_devices[dev][channel].mutereg;
538 change_bits(devc, &val, &muteval, dev, channel, value);
541 change_bits(devc, &val, &val, dev, channel, value);
585 * Set the left channel
590 * Set the right channel
2665 * Handle the capture DMA channel
2931 MODULE_PARM(dma, "i"); /* First DMA channel */
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/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/net/wan/8253x/
H A D8253xini.c2892 unsigned int channel;
2901 channel = (((unsigned char*) port->regs) - bptr->CIMCMD_REG); /* should be properly shifted */
2908 writeb((unsigned char) wcount, bptr->MICCMD_REG + (MICCMD_CACHETRIG + channel));
2914 channel >>= 1;
2918 fifo[i] = readw((unsigned short*)(bptr->FIFOCACHE_REG + (channel + (i << 1))));
/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/scsi/
H A Dips.c1756 SC->channel,
1761 if ((SC->channel > 0) && (SC->target == ha->ha_id[SC->channel])) {
1906 if ((device->channel == 0) && (device->type == 0))
1913 if ((device->channel == 0) && (device->type == 0)) {
2222 (SC->channel == 0) &&
2521 scb->bus = scb->scsi_cmd->channel;
2580 scb->bus = scb->scsi_cmd->channel;
3322 if ((p->channel > 0) && (ha->dcdb_active[p->channel
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H A Dpci2000.c419 UCHAR bus = SCpnt->channel;
H A Dpsi240i.c627 unit = chipDevice[z].channel & 0x0F;
/asus-wl-520gu-7.0.1.45/src/bcm57xx/sys/
H A Dtigon3.c358 * with the other channel loading boot code.
6843 /* Deselect the channel register so we can read the PHY id later. */
8081 int i, channel; local
8138 for (channel=0; (channel<4) && (reset_success == LM_STATUS_SUCCESS);
8139 channel++)
8141 /* select channel and set TAP index to 0 */
8142 LM_WritePhy(pDevice, 0x17, (channel * 0x2000) | 0x0200);
8147 each channel, each TAP have 2 WORDs (LO/HI) */
8149 LM_WritePhy(pDevice, 0x15, pattern[channel][
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/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/ieee1394/
H A Dpcilynx.c437 run_pcl(lynx, d->pcl_start, d->channel);
1379 lynx->async.channel = CHANNEL_ASYNC_SEND;
1381 lynx->iso_send.channel = CHANNEL_ISO_SEND;
/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/scsi/aacraid/
H A Daachba.c879 if ((scsicmd->channel == 0) ){
1426 srbcmd->channel = cpu_to_le32(aac_logical_to_phys(scsicmd->channel));
/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/s390/boot/
H A Dipleckd.S212 tm .Lirb+9,0xff # channel status ?
/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/s390x/boot/
H A Dipleckd.S212 tm .Lirb+9,0xff # channel status ?
/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/ide/
H A Dcmd640.c804 cmd_hwif1->channel = 1;
/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/isdn/avmb1/
H A Dcapidrv.c943 * HL-driver may send ALERTING on the D-channel in this
1553 /* Channel: 3 => use channel allocation */
1764 printk(KERN_ERR "capidrv-%d: chan %ld disconnect request on free channel\n",
1867 static int if_sendbuf(int id, int channel, int doack, struct sk_buff *skb) argument
1885 bchan = &card->bchans[channel % card->nbchan];
1889 card->contrnr, card->name, channel);
1941 static int if_readstat(__u8 *buf, int len, int user, int id, int channel) argument
1980 printk(KERN_ERR "%s: not from AVM, no d-channel trace possible (%s)\n",
/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/sbus/char/
H A Daurora.c451 unsigned char channel; local
454 channel = ((chip << 3) |
456 port = &aurora_port[board_No(bp) * AURORA_NPORT * AURORA_NCD180 + channel];
461 board_No(bp), what, channel);
1069 /* Setting up CD180 channel registers */
/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/usb/
H A Dhpusbscsi.c351 if ( srb->device->lun || srb->device->id || srb->device->channel ) {
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/linux/
H A Dcyclades.h298 /* channel op_mode */
300 #define C_CH_DISABLE 0x00000000 /* channel is disabled */
301 #define C_CH_TXENABLE 0x00000001 /* channel Tx enabled */
302 #define C_CH_RXENABLE 0x00000002 /* channel Rx enabled */
303 #define C_CH_ENABLE 0x00000003 /* channel Tx/Rx enabled */
450 * BUF_CTRL - This per channel structure contains
451 * all Tx and Rx buffer control for a given channel.
488 uclong hcmd_channel; /* channel number */
492 uclong fwcmd_channel; /* channel number */
506 unsigned long channel[QUEUE_SIZ member in struct:INT_QUEUE
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/asus-wl-520gu-7.0.1.45/src/linux/linux/include/linux/
H A Dcyclades.h295 /* channel op_mode */
297 #define C_CH_DISABLE 0x00000000 /* channel is disabled */
298 #define C_CH_TXENABLE 0x00000001 /* channel Tx enabled */
299 #define C_CH_RXENABLE 0x00000002 /* channel Rx enabled */
300 #define C_CH_ENABLE 0x00000003 /* channel Tx/Rx enabled */
447 * BUF_CTRL - This per channel structure contains
448 * all Tx and Rx buffer control for a given channel.
485 uclong hcmd_channel; /* channel number */
489 uclong fwcmd_channel; /* channel number */
503 unsigned long channel[QUEUE_SIZ member in struct:INT_QUEUE
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