1/* $Revision: 1.1.1.1 $$Date: 2008/10/15 03:27:30 $ 2 * linux/include/linux/cyclades.h 3 * 4 * This file was initially written by 5 * Randolph Bentson <bentson@grieg.seaslug.org> and is maintained by 6 * Ivan Passos <ivan@cyclades.com>. 7 * 8 * This file contains the general definitions for the cyclades.c driver 9 *$Log: cyclades.h,v $ 10 *Revision 1.1.1.1 2008/10/15 03:27:30 james26_jang 11 *Initial. 12 * 13 *Revision 1.1.1.1 2008/07/21 09:16:05 james26_jang 14 *New UI, New QoS, New wireless driver(4.151.10.29), ipmonitor. 15 * 16 *Revision 1.1.1.1 2008/07/02 14:40:28 james26_jang 17 *4.100.10.29, New QoS and New UI. 18 * 19 *Revision 1.1.1.1 2007/02/15 12:12:31 jiahao 20 *initial update 21 * 22 *Revision 1.1.1.1 2007/01/25 12:52:07 jiahao_jhou 23 * 24 * 25 *Revision 1.1.1.1 2003/02/03 22:38:16 mhuang 26 *LINUX_2_4 branch snapshot from linux-mips.org CVS 27 * 28 *Revision 3.1 2000/04/19 18:52:52 ivan 29 *converted address fields to unsigned long and added fields for physical 30 *addresses on cyclades_card structure; 31 * 32 *Revision 3.0 1998/11/02 14:20:59 ivan 33 *added nports field on cyclades_card structure; 34 * 35 *Revision 2.5 1998/08/03 16:57:01 ivan 36 *added cyclades_idle_stats structure; 37 * 38 *Revision 2.4 1998/06/01 12:09:53 ivan 39 *removed closing_wait2 from cyclades_port structure; 40 * 41 *Revision 2.3 1998/03/16 18:01:12 ivan 42 *changes in the cyclades_port structure to get it closer to the 43 *standard serial port structure; 44 *added constants for new ioctls; 45 * 46 *Revision 2.2 1998/02/17 16:50:00 ivan 47 *changes in the cyclades_port structure (addition of shutdown_wait and 48 *chip_rev variables); 49 *added constants for new ioctls and for CD1400 rev. numbers. 50 * 51 *Revision 2.1 1997/10/24 16:03:00 ivan 52 *added rflow (which allows enabling the CD1400 special flow control 53 *feature) and rtsdtr_inv (which allows DTR/RTS pin inversion) to 54 *cyclades_port structure; 55 *added Alpha support 56 * 57 *Revision 2.0 1997/06/30 10:30:00 ivan 58 *added some new doorbell command constants related to IOCTLW and 59 *UART error signaling 60 * 61 *Revision 1.8 1997/06/03 15:30:00 ivan 62 *added constant ZFIRM_HLT 63 *added constant CyPCI_Ze_win ( = 2 * Cy_PCI_Zwin) 64 * 65 *Revision 1.7 1997/03/26 10:30:00 daniel 66 *new entries at the end of cyclades_port struct to reallocate 67 *variables illegally allocated within card memory. 68 * 69 *Revision 1.6 1996/09/09 18:35:30 bentson 70 *fold in changes for Cyclom-Z -- including structures for 71 *communicating with board as well modest changes to original 72 *structures to support new features. 73 * 74 *Revision 1.5 1995/11/13 21:13:31 bentson 75 *changes suggested by Michael Chastain <mec@duracef.shout.net> 76 *to support use of this file in non-kernel applications 77 * 78 * 79 */ 80 81#ifndef _LINUX_CYCLADES_H 82#define _LINUX_CYCLADES_H 83 84struct cyclades_monitor { 85 unsigned long int_count; 86 unsigned long char_count; 87 unsigned long char_max; 88 unsigned long char_last; 89}; 90 91/* 92 * These stats all reflect activity since the device was last initialized. 93 * (i.e., since the port was opened with no other processes already having it 94 * open) 95 */ 96struct cyclades_idle_stats { 97 time_t in_use; /* Time device has been in use (secs) */ 98 time_t recv_idle; /* Time since last char received (secs) */ 99 time_t xmit_idle; /* Time since last char transmitted (secs) */ 100 unsigned long recv_bytes; /* Bytes received */ 101 unsigned long xmit_bytes; /* Bytes transmitted */ 102 unsigned long overruns; /* Input overruns */ 103 unsigned long frame_errs; /* Input framing errors */ 104 unsigned long parity_errs; /* Input parity errors */ 105}; 106 107#define CYCLADES_MAGIC 0x4359 108 109#define CYGETMON 0x435901 110#define CYGETTHRESH 0x435902 111#define CYSETTHRESH 0x435903 112#define CYGETDEFTHRESH 0x435904 113#define CYSETDEFTHRESH 0x435905 114#define CYGETTIMEOUT 0x435906 115#define CYSETTIMEOUT 0x435907 116#define CYGETDEFTIMEOUT 0x435908 117#define CYSETDEFTIMEOUT 0x435909 118#define CYSETRFLOW 0x43590a 119#define CYGETRFLOW 0x43590b 120#define CYSETRTSDTR_INV 0x43590c 121#define CYGETRTSDTR_INV 0x43590d 122#define CYZSETPOLLCYCLE 0x43590e 123#define CYZGETPOLLCYCLE 0x43590f 124#define CYGETCD1400VER 0x435910 125#define CYGETCARDINFO 0x435911 126#define CYSETWAIT 0x435912 127#define CYGETWAIT 0x435913 128 129/*************** CYCLOM-Z ADDITIONS ***************/ 130 131#define CZIOC ('M' << 8) 132#define CZ_NBOARDS (CZIOC|0xfa) 133#define CZ_BOOT_START (CZIOC|0xfb) 134#define CZ_BOOT_DATA (CZIOC|0xfc) 135#define CZ_BOOT_END (CZIOC|0xfd) 136#define CZ_TEST (CZIOC|0xfe) 137 138#define CZ_DEF_POLL (HZ/25) 139 140#define MAX_BOARD 4 /* Max number of boards */ 141#define MAX_DEV 256 /* Max number of ports total */ 142#define CYZ_MAX_SPEED 921600 143 144#define CYZ_FIFO_SIZE 16 145 146#define CYZ_BOOT_NWORDS 0x100 147struct CYZ_BOOT_CTRL { 148 unsigned short nboard; 149 int status[MAX_BOARD]; 150 int nchannel[MAX_BOARD]; 151 int fw_rev[MAX_BOARD]; 152 unsigned long offset; 153 unsigned long data[CYZ_BOOT_NWORDS]; 154}; 155 156 157#ifndef DP_WINDOW_SIZE 158/* #include "cyclomz.h" */ 159/****************** ****************** *******************/ 160/* 161 * The data types defined below are used in all ZFIRM interface 162 * data structures. They accomodate differences between HW 163 * architectures and compilers. 164 */ 165 166#if defined(__alpha__) 167typedef unsigned long ucdouble; /* 64 bits, unsigned */ 168typedef unsigned int uclong; /* 32 bits, unsigned */ 169#else 170typedef unsigned long uclong; /* 32 bits, unsigned */ 171#endif 172typedef unsigned short ucshort; /* 16 bits, unsigned */ 173typedef unsigned char ucchar; /* 8 bits, unsigned */ 174 175/* 176 * Memory Window Sizes 177 */ 178 179#define DP_WINDOW_SIZE (0x00080000) /* window size 512 Kb */ 180#define ZE_DP_WINDOW_SIZE (0x00100000) /* window size 1 Mb (Ze and 181 8Zo V.2 */ 182#define CTRL_WINDOW_SIZE (0x00000080) /* runtime regs 128 bytes */ 183 184/* 185 * CUSTOM_REG - Cyclom-Z/PCI Custom Registers Set. The driver 186 * normally will access only interested on the fpga_id, fpga_version, 187 * start_cpu and stop_cpu. 188 */ 189 190struct CUSTOM_REG { 191 uclong fpga_id; /* FPGA Identification Register */ 192 uclong fpga_version; /* FPGA Version Number Register */ 193 uclong cpu_start; /* CPU start Register (write) */ 194 uclong cpu_stop; /* CPU stop Register (write) */ 195 uclong misc_reg; /* Miscelaneous Register */ 196 uclong idt_mode; /* IDT mode Register */ 197 uclong uart_irq_status; /* UART IRQ status Register */ 198 uclong clear_timer0_irq; /* Clear timer interrupt Register */ 199 uclong clear_timer1_irq; /* Clear timer interrupt Register */ 200 uclong clear_timer2_irq; /* Clear timer interrupt Register */ 201 uclong test_register; /* Test Register */ 202 uclong test_count; /* Test Count Register */ 203 uclong timer_select; /* Timer select register */ 204 uclong pr_uart_irq_status; /* Prioritized UART IRQ stat Reg */ 205 uclong ram_wait_state; /* RAM wait-state Register */ 206 uclong uart_wait_state; /* UART wait-state Register */ 207 uclong timer_wait_state; /* timer wait-state Register */ 208 uclong ack_wait_state; /* ACK wait State Register */ 209}; 210 211/* 212 * RUNTIME_9060 - PLX PCI9060ES local configuration and shared runtime 213 * registers. This structure can be used to access the 9060 registers 214 * (memory mapped). 215 */ 216 217struct RUNTIME_9060 { 218 uclong loc_addr_range; /* 00h - Local Address Range */ 219 uclong loc_addr_base; /* 04h - Local Address Base */ 220 uclong loc_arbitr; /* 08h - Local Arbitration */ 221 uclong endian_descr; /* 0Ch - Big/Little Endian Descriptor */ 222 uclong loc_rom_range; /* 10h - Local ROM Range */ 223 uclong loc_rom_base; /* 14h - Local ROM Base */ 224 uclong loc_bus_descr; /* 18h - Local Bus descriptor */ 225 uclong loc_range_mst; /* 1Ch - Local Range for Master to PCI */ 226 uclong loc_base_mst; /* 20h - Local Base for Master PCI */ 227 uclong loc_range_io; /* 24h - Local Range for Master IO */ 228 uclong pci_base_mst; /* 28h - PCI Base for Master PCI */ 229 uclong pci_conf_io; /* 2Ch - PCI configuration for Master IO */ 230 uclong filler1; /* 30h */ 231 uclong filler2; /* 34h */ 232 uclong filler3; /* 38h */ 233 uclong filler4; /* 3Ch */ 234 uclong mail_box_0; /* 40h - Mail Box 0 */ 235 uclong mail_box_1; /* 44h - Mail Box 1 */ 236 uclong mail_box_2; /* 48h - Mail Box 2 */ 237 uclong mail_box_3; /* 4Ch - Mail Box 3 */ 238 uclong filler5; /* 50h */ 239 uclong filler6; /* 54h */ 240 uclong filler7; /* 58h */ 241 uclong filler8; /* 5Ch */ 242 uclong pci_doorbell; /* 60h - PCI to Local Doorbell */ 243 uclong loc_doorbell; /* 64h - Local to PCI Doorbell */ 244 uclong intr_ctrl_stat; /* 68h - Interrupt Control/Status */ 245 uclong init_ctrl; /* 6Ch - EEPROM control, Init Control, etc */ 246}; 247 248/* Values for the Local Base Address re-map register */ 249 250#define WIN_RAM 0x00000001L /* set the sliding window to RAM */ 251#define WIN_CREG 0x14000001L /* set the window to custom Registers */ 252 253/* Values timer select registers */ 254 255#define TIMER_BY_1M 0x00 /* clock divided by 1M */ 256#define TIMER_BY_256K 0x01 /* clock divided by 256k */ 257#define TIMER_BY_128K 0x02 /* clock divided by 128k */ 258#define TIMER_BY_32K 0x03 /* clock divided by 32k */ 259 260/****************** ****************** *******************/ 261#endif 262 263#ifndef ZFIRM_ID 264/* #include "zfwint.h" */ 265/****************** ****************** *******************/ 266/* 267 * This file contains the definitions for interfacing with the 268 * Cyclom-Z ZFIRM Firmware. 269 */ 270 271/* General Constant definitions */ 272 273#define MAX_CHAN 64 /* max number of channels per board */ 274 275/* firmware id structure (set after boot) */ 276 277#define ID_ADDRESS 0x00000180L /* signature/pointer address */ 278#define ZFIRM_ID 0x5557465AL /* ZFIRM/U signature */ 279#define ZFIRM_HLT 0x59505B5CL /* ZFIRM needs external power supply */ 280#define ZFIRM_RST 0x56040674L /* RST signal (due to FW reset) */ 281 282#define ZF_TINACT_DEF 1000 /* default inactivity timeout 283 (1000 ms) */ 284#define ZF_TINACT ZF_TINACT_DEF 285 286struct FIRM_ID { 287 uclong signature; /* ZFIRM/U signature */ 288 uclong zfwctrl_addr; /* pointer to ZFW_CTRL structure */ 289}; 290 291/* Op. System id */ 292 293#define C_OS_LINUX 0x00000030 /* generic Linux system */ 294 295/* channel op_mode */ 296 297#define C_CH_DISABLE 0x00000000 /* channel is disabled */ 298#define C_CH_TXENABLE 0x00000001 /* channel Tx enabled */ 299#define C_CH_RXENABLE 0x00000002 /* channel Rx enabled */ 300#define C_CH_ENABLE 0x00000003 /* channel Tx/Rx enabled */ 301#define C_CH_LOOPBACK 0x00000004 /* Loopback mode */ 302 303/* comm_parity - parity */ 304 305#define C_PR_NONE 0x00000000 /* None */ 306#define C_PR_ODD 0x00000001 /* Odd */ 307#define C_PR_EVEN 0x00000002 /* Even */ 308#define C_PR_MARK 0x00000004 /* Mark */ 309#define C_PR_SPACE 0x00000008 /* Space */ 310#define C_PR_PARITY 0x000000ff 311 312#define C_PR_DISCARD 0x00000100 /* discard char with frame/par error */ 313#define C_PR_IGNORE 0x00000200 /* ignore frame/par error */ 314 315/* comm_data_l - data length and stop bits */ 316 317#define C_DL_CS5 0x00000001 318#define C_DL_CS6 0x00000002 319#define C_DL_CS7 0x00000004 320#define C_DL_CS8 0x00000008 321#define C_DL_CS 0x0000000f 322#define C_DL_1STOP 0x00000010 323#define C_DL_15STOP 0x00000020 324#define C_DL_2STOP 0x00000040 325#define C_DL_STOP 0x000000f0 326 327/* interrupt enabling/status */ 328 329#define C_IN_DISABLE 0x00000000 /* zero, disable interrupts */ 330#define C_IN_TXBEMPTY 0x00000001 /* tx buffer empty */ 331#define C_IN_TXLOWWM 0x00000002 /* tx buffer below LWM */ 332#define C_IN_RXHIWM 0x00000010 /* rx buffer above HWM */ 333#define C_IN_RXNNDT 0x00000020 /* rx no new data timeout */ 334#define C_IN_MDCD 0x00000100 /* modem DCD change */ 335#define C_IN_MDSR 0x00000200 /* modem DSR change */ 336#define C_IN_MRI 0x00000400 /* modem RI change */ 337#define C_IN_MCTS 0x00000800 /* modem CTS change */ 338#define C_IN_RXBRK 0x00001000 /* Break received */ 339#define C_IN_PR_ERROR 0x00002000 /* parity error */ 340#define C_IN_FR_ERROR 0x00004000 /* frame error */ 341#define C_IN_OVR_ERROR 0x00008000 /* overrun error */ 342#define C_IN_RXOFL 0x00010000 /* RX buffer overflow */ 343#define C_IN_IOCTLW 0x00020000 /* I/O control w/ wait */ 344#define C_IN_MRTS 0x00040000 /* modem RTS drop */ 345#define C_IN_ICHAR 0x00080000 346 347/* flow control */ 348 349#define C_FL_OXX 0x00000001 /* output Xon/Xoff flow control */ 350#define C_FL_IXX 0x00000002 /* output Xon/Xoff flow control */ 351#define C_FL_OIXANY 0x00000004 /* output Xon/Xoff (any xon) */ 352#define C_FL_SWFLOW 0x0000000f 353 354/* flow status */ 355 356#define C_FS_TXIDLE 0x00000000 /* no Tx data in the buffer or UART */ 357#define C_FS_SENDING 0x00000001 /* UART is sending data */ 358#define C_FS_SWFLOW 0x00000002 /* Tx is stopped by received Xoff */ 359 360/* rs_control/rs_status RS-232 signals */ 361 362#define C_RS_PARAM 0x80000000 /* Indicates presence of parameter in 363 IOCTLM command */ 364#define C_RS_RTS 0x00000001 /* RTS */ 365#define C_RS_DTR 0x00000004 /* DTR */ 366#define C_RS_DCD 0x00000100 /* CD */ 367#define C_RS_DSR 0x00000200 /* DSR */ 368#define C_RS_RI 0x00000400 /* RI */ 369#define C_RS_CTS 0x00000800 /* CTS */ 370 371/* commands Host <-> Board */ 372 373#define C_CM_RESET 0x01 /* reset/flush buffers */ 374#define C_CM_IOCTL 0x02 /* re-read CH_CTRL */ 375#define C_CM_IOCTLW 0x03 /* re-read CH_CTRL, intr when done */ 376#define C_CM_IOCTLM 0x04 /* RS-232 outputs change */ 377#define C_CM_SENDXOFF 0x10 /* send Xoff */ 378#define C_CM_SENDXON 0x11 /* send Xon */ 379#define C_CM_CLFLOW 0x12 /* Clear flow control (resume) */ 380#define C_CM_SENDBRK 0x41 /* send break */ 381#define C_CM_INTBACK 0x42 /* Interrupt back */ 382#define C_CM_SET_BREAK 0x43 /* Tx break on */ 383#define C_CM_CLR_BREAK 0x44 /* Tx break off */ 384#define C_CM_CMD_DONE 0x45 /* Previous command done */ 385#define C_CM_INTBACK2 0x46 /* Alternate Interrupt back */ 386#define C_CM_TINACT 0x51 /* set inactivity detection */ 387#define C_CM_IRQ_ENBL 0x52 /* enable generation of interrupts */ 388#define C_CM_IRQ_DSBL 0x53 /* disable generation of interrupts */ 389#define C_CM_ACK_ENBL 0x54 /* enable acknowledged interrupt mode */ 390#define C_CM_ACK_DSBL 0x55 /* disable acknowledged intr mode */ 391#define C_CM_FLUSH_RX 0x56 /* flushes Rx buffer */ 392#define C_CM_FLUSH_TX 0x57 /* flushes Tx buffer */ 393#define C_CM_Q_ENABLE 0x58 /* enables queue access from the 394 driver */ 395#define C_CM_Q_DISABLE 0x59 /* disables queue access from the 396 driver */ 397 398#define C_CM_TXBEMPTY 0x60 /* Tx buffer is empty */ 399#define C_CM_TXLOWWM 0x61 /* Tx buffer low water mark */ 400#define C_CM_RXHIWM 0x62 /* Rx buffer high water mark */ 401#define C_CM_RXNNDT 0x63 /* rx no new data timeout */ 402#define C_CM_TXFEMPTY 0x64 403#define C_CM_ICHAR 0x65 404#define C_CM_MDCD 0x70 /* modem DCD change */ 405#define C_CM_MDSR 0x71 /* modem DSR change */ 406#define C_CM_MRI 0x72 /* modem RI change */ 407#define C_CM_MCTS 0x73 /* modem CTS change */ 408#define C_CM_MRTS 0x74 /* modem RTS drop */ 409#define C_CM_RXBRK 0x84 /* Break received */ 410#define C_CM_PR_ERROR 0x85 /* Parity error */ 411#define C_CM_FR_ERROR 0x86 /* Frame error */ 412#define C_CM_OVR_ERROR 0x87 /* Overrun error */ 413#define C_CM_RXOFL 0x88 /* RX buffer overflow */ 414#define C_CM_CMDERROR 0x90 /* command error */ 415#define C_CM_FATAL 0x91 /* fatal error */ 416#define C_CM_HW_RESET 0x92 /* reset board */ 417 418/* 419 * CH_CTRL - This per port structure contains all parameters 420 * that control an specific port. It can be seen as the 421 * configuration registers of a "super-serial-controller". 422 */ 423 424struct CH_CTRL { 425 uclong op_mode; /* operation mode */ 426 uclong intr_enable; /* interrupt masking */ 427 uclong sw_flow; /* SW flow control */ 428 uclong flow_status; /* output flow status */ 429 uclong comm_baud; /* baud rate - numerically specified */ 430 uclong comm_parity; /* parity */ 431 uclong comm_data_l; /* data length/stop */ 432 uclong comm_flags; /* other flags */ 433 uclong hw_flow; /* HW flow control */ 434 uclong rs_control; /* RS-232 outputs */ 435 uclong rs_status; /* RS-232 inputs */ 436 uclong flow_xon; /* xon char */ 437 uclong flow_xoff; /* xoff char */ 438 uclong hw_overflow; /* hw overflow counter */ 439 uclong sw_overflow; /* sw overflow counter */ 440 uclong comm_error; /* frame/parity error counter */ 441 uclong ichar; 442 uclong filler[7]; 443}; 444 445 446/* 447 * BUF_CTRL - This per channel structure contains 448 * all Tx and Rx buffer control for a given channel. 449 */ 450 451struct BUF_CTRL { 452 uclong flag_dma; /* buffers are in Host memory */ 453 uclong tx_bufaddr; /* address of the tx buffer */ 454 uclong tx_bufsize; /* tx buffer size */ 455 uclong tx_threshold; /* tx low water mark */ 456 uclong tx_get; /* tail index tx buf */ 457 uclong tx_put; /* head index tx buf */ 458 uclong rx_bufaddr; /* address of the rx buffer */ 459 uclong rx_bufsize; /* rx buffer size */ 460 uclong rx_threshold; /* rx high water mark */ 461 uclong rx_get; /* tail index rx buf */ 462 uclong rx_put; /* head index rx buf */ 463 uclong filler[5]; /* filler to align structures */ 464}; 465 466/* 467 * BOARD_CTRL - This per board structure contains all global 468 * control fields related to the board. 469 */ 470 471struct BOARD_CTRL { 472 473 /* static info provided by the on-board CPU */ 474 uclong n_channel; /* number of channels */ 475 uclong fw_version; /* firmware version */ 476 477 /* static info provided by the driver */ 478 uclong op_system; /* op_system id */ 479 uclong dr_version; /* driver version */ 480 481 /* board control area */ 482 uclong inactivity; /* inactivity control */ 483 484 /* host to FW commands */ 485 uclong hcmd_channel; /* channel number */ 486 uclong hcmd_param; /* pointer to parameters */ 487 488 /* FW to Host commands */ 489 uclong fwcmd_channel; /* channel number */ 490 uclong fwcmd_param; /* pointer to parameters */ 491 uclong zf_int_queue_addr; /* offset for INT_QUEUE structure */ 492 493 /* filler so the structures are aligned */ 494 uclong filler[6]; 495}; 496 497/* Host Interrupt Queue */ 498 499#define QUEUE_SIZE (10*MAX_CHAN) 500 501struct INT_QUEUE { 502 unsigned char intr_code[QUEUE_SIZE]; 503 unsigned long channel[QUEUE_SIZE]; 504 unsigned long param[QUEUE_SIZE]; 505 unsigned long put; 506 unsigned long get; 507}; 508 509/* 510 * ZFW_CTRL - This is the data structure that includes all other 511 * data structures used by the Firmware. 512 */ 513 514struct ZFW_CTRL { 515 struct BOARD_CTRL board_ctrl; 516 struct CH_CTRL ch_ctrl[MAX_CHAN]; 517 struct BUF_CTRL buf_ctrl[MAX_CHAN]; 518}; 519 520/****************** ****************** *******************/ 521#endif 522 523/* Per card data structure */ 524struct cyclades_card { 525 unsigned long base_phys; 526 unsigned long ctl_phys; 527 unsigned long base_addr; 528 unsigned long ctl_addr; 529 int irq; 530 int num_chips; /* 0 if card absent, -1 if Z/PCI, else Y */ 531 int first_line; /* minor number of first channel on card */ 532 int nports; /* Number of ports in the card */ 533 int bus_index; /* address shift - 0 for ISA, 1 for PCI */ 534 int intr_enabled; /* FW Interrupt flag - 0 disabled, 1 enabled */ 535 struct resource *resource; 536 unsigned long res_start; 537 unsigned long res_len; 538#ifdef __KERNEL__ 539 spinlock_t card_lock; 540#else 541 unsigned long filler; 542#endif 543}; 544 545struct cyclades_chip { 546 int filler; 547}; 548 549 550#ifdef __KERNEL__ 551 552/*************************************** 553 * Memory access functions/macros * 554 * (required to support Alpha systems) * 555 ***************************************/ 556 557#define cy_writeb(port,val) {writeb((ucchar)(val),(ulong)(port)); mb();} 558#define cy_writew(port,val) {writew((ushort)(val),(ulong)(port)); mb();} 559#define cy_writel(port,val) {writel((uclong)(val),(ulong)(port)); mb();} 560 561#define cy_readb(port) readb(port) 562#define cy_readw(port) readw(port) 563#define cy_readl(port) readl(port) 564 565/* 566 * Statistics counters 567 */ 568struct cyclades_icount { 569 __u32 cts, dsr, rng, dcd, tx, rx; 570 __u32 frame, parity, overrun, brk; 571 __u32 buf_overrun; 572}; 573 574/* 575 * This is our internal structure for each serial port's state. 576 * 577 * Many fields are paralleled by the structure used by the serial_struct 578 * structure. 579 * 580 * For definitions of the flags field, see tty.h 581 */ 582 583struct cyclades_port { 584 int magic; 585 int card; 586 int line; 587 int flags; /* defined in tty.h */ 588 int type; /* UART type */ 589 struct tty_struct *tty; 590 int read_status_mask; 591 int ignore_status_mask; 592 int timeout; 593 int xmit_fifo_size; 594 int cor1,cor2,cor3,cor4,cor5; 595 int tbpr,tco,rbpr,rco; 596 int baud; 597 int rflow; 598 int rtsdtr_inv; 599 int chip_rev; 600 int custom_divisor; 601 int x_char; /* to be pushed out ASAP */ 602 int close_delay; 603 unsigned short closing_wait; 604 unsigned long event; 605 unsigned long last_active; 606 int count; /* # of fd on device */ 607 int breakon; 608 int breakoff; 609 int blocked_open; /* # of blocked opens */ 610 long session; /* Session of opening process */ 611 long pgrp; /* pgrp of opening process */ 612 unsigned char *xmit_buf; 613 int xmit_head; 614 int xmit_tail; 615 int xmit_cnt; 616 int default_threshold; 617 int default_timeout; 618 unsigned long jiffies[3]; 619 unsigned long rflush_count; 620 struct termios normal_termios; 621 struct termios callout_termios; 622 struct cyclades_monitor mon; 623 struct cyclades_idle_stats idle_stats; 624 struct cyclades_icount icount; 625 struct tq_struct tqueue; 626 wait_queue_head_t open_wait; 627 wait_queue_head_t close_wait; 628 wait_queue_head_t shutdown_wait; 629 wait_queue_head_t delta_msr_wait; 630}; 631 632/* 633 * Events are used to schedule things to happen at timer-interrupt 634 * time, instead of at cy interrupt time. 635 */ 636#define Cy_EVENT_READ_PROCESS 0 637#define Cy_EVENT_WRITE_WAKEUP 1 638#define Cy_EVENT_HANGUP 2 639#define Cy_EVENT_BREAK 3 640#define Cy_EVENT_OPEN_WAKEUP 4 641#define Cy_EVENT_SHUTDOWN_WAKEUP 5 642#define Cy_EVENT_DELTA_WAKEUP 6 643#define Cy_EVENT_Z_RX_FULL 7 644 645#define CLOSING_WAIT_DELAY 30*HZ 646#define CY_CLOSING_WAIT_NONE 65535 647#define CY_CLOSING_WAIT_INF 0 648 649 650#define CyMAX_CHIPS_PER_CARD 8 651#define CyMAX_CHAR_FIFO 12 652#define CyPORTS_PER_CHIP 4 653#define CD1400_MAX_SPEED 115200 654 655#define CyISA_Ywin 0x2000 656 657#define CyPCI_Ywin 0x4000 658#define CyPCI_Yctl 0x80 659#define CyPCI_Zctl CTRL_WINDOW_SIZE 660#define CyPCI_Zwin 0x80000 661#define CyPCI_Ze_win (2 * CyPCI_Zwin) 662 663#define PCI_DEVICE_ID_MASK 0x06 664 665/**** CD1400 registers ****/ 666 667#define CD1400_REV_G 0x46 668#define CD1400_REV_J 0x48 669 670#define CyRegSize 0x0400 671#define Cy_HwReset 0x1400 672#define Cy_ClrIntr 0x1800 673#define Cy_EpldRev 0x1e00 674 675/* Global Registers */ 676 677#define CyGFRCR (0x40*2) 678#define CyRevE (44) 679#define CyCAR (0x68*2) 680#define CyCHAN_0 (0x00) 681#define CyCHAN_1 (0x01) 682#define CyCHAN_2 (0x02) 683#define CyCHAN_3 (0x03) 684#define CyGCR (0x4B*2) 685#define CyCH0_SERIAL (0x00) 686#define CyCH0_PARALLEL (0x80) 687#define CySVRR (0x67*2) 688#define CySRModem (0x04) 689#define CySRTransmit (0x02) 690#define CySRReceive (0x01) 691#define CyRICR (0x44*2) 692#define CyTICR (0x45*2) 693#define CyMICR (0x46*2) 694#define CyICR0 (0x00) 695#define CyICR1 (0x01) 696#define CyICR2 (0x02) 697#define CyICR3 (0x03) 698#define CyRIR (0x6B*2) 699#define CyTIR (0x6A*2) 700#define CyMIR (0x69*2) 701#define CyIRDirEq (0x80) 702#define CyIRBusy (0x40) 703#define CyIRUnfair (0x20) 704#define CyIRContext (0x1C) 705#define CyIRChannel (0x03) 706#define CyPPR (0x7E*2) 707#define CyCLOCK_20_1MS (0x27) 708#define CyCLOCK_25_1MS (0x31) 709#define CyCLOCK_25_5MS (0xf4) 710#define CyCLOCK_60_1MS (0x75) 711#define CyCLOCK_60_2MS (0xea) 712 713/* Virtual Registers */ 714 715#define CyRIVR (0x43*2) 716#define CyTIVR (0x42*2) 717#define CyMIVR (0x41*2) 718#define CyIVRMask (0x07) 719#define CyIVRRxEx (0x07) 720#define CyIVRRxOK (0x03) 721#define CyIVRTxOK (0x02) 722#define CyIVRMdmOK (0x01) 723#define CyTDR (0x63*2) 724#define CyRDSR (0x62*2) 725#define CyTIMEOUT (0x80) 726#define CySPECHAR (0x70) 727#define CyBREAK (0x08) 728#define CyPARITY (0x04) 729#define CyFRAME (0x02) 730#define CyOVERRUN (0x01) 731#define CyMISR (0x4C*2) 732/* see CyMCOR_ and CyMSVR_ for bits*/ 733#define CyEOSRR (0x60*2) 734 735/* Channel Registers */ 736 737#define CyLIVR (0x18*2) 738#define CyMscsr (0x01) 739#define CyTdsr (0x02) 740#define CyRgdsr (0x03) 741#define CyRedsr (0x07) 742#define CyCCR (0x05*2) 743/* Format 1 */ 744#define CyCHAN_RESET (0x80) 745#define CyCHIP_RESET (0x81) 746#define CyFlushTransFIFO (0x82) 747/* Format 2 */ 748#define CyCOR_CHANGE (0x40) 749#define CyCOR1ch (0x02) 750#define CyCOR2ch (0x04) 751#define CyCOR3ch (0x08) 752/* Format 3 */ 753#define CySEND_SPEC_1 (0x21) 754#define CySEND_SPEC_2 (0x22) 755#define CySEND_SPEC_3 (0x23) 756#define CySEND_SPEC_4 (0x24) 757/* Format 4 */ 758#define CyCHAN_CTL (0x10) 759#define CyDIS_RCVR (0x01) 760#define CyENB_RCVR (0x02) 761#define CyDIS_XMTR (0x04) 762#define CyENB_XMTR (0x08) 763#define CySRER (0x06*2) 764#define CyMdmCh (0x80) 765#define CyRxData (0x10) 766#define CyTxRdy (0x04) 767#define CyTxMpty (0x02) 768#define CyNNDT (0x01) 769#define CyCOR1 (0x08*2) 770#define CyPARITY_NONE (0x00) 771#define CyPARITY_0 (0x20) 772#define CyPARITY_1 (0xA0) 773#define CyPARITY_E (0x40) 774#define CyPARITY_O (0xC0) 775#define Cy_1_STOP (0x00) 776#define Cy_1_5_STOP (0x04) 777#define Cy_2_STOP (0x08) 778#define Cy_5_BITS (0x00) 779#define Cy_6_BITS (0x01) 780#define Cy_7_BITS (0x02) 781#define Cy_8_BITS (0x03) 782#define CyCOR2 (0x09*2) 783#define CyIXM (0x80) 784#define CyTxIBE (0x40) 785#define CyETC (0x20) 786#define CyAUTO_TXFL (0x60) 787#define CyLLM (0x10) 788#define CyRLM (0x08) 789#define CyRtsAO (0x04) 790#define CyCtsAE (0x02) 791#define CyDsrAE (0x01) 792#define CyCOR3 (0x0A*2) 793#define CySPL_CH_DRANGE (0x80) /* special character detect range */ 794#define CySPL_CH_DET1 (0x40) /* enable special character detection 795 on SCHR4-SCHR3 */ 796#define CyFL_CTRL_TRNSP (0x20) /* Flow Control Transparency */ 797#define CySPL_CH_DET2 (0x10) /* Enable special character detection 798 on SCHR2-SCHR1 */ 799#define CyREC_FIFO (0x0F) /* Receive FIFO threshold */ 800#define CyCOR4 (0x1E*2) 801#define CyCOR5 (0x1F*2) 802#define CyCCSR (0x0B*2) 803#define CyRxEN (0x80) 804#define CyRxFloff (0x40) 805#define CyRxFlon (0x20) 806#define CyTxEN (0x08) 807#define CyTxFloff (0x04) 808#define CyTxFlon (0x02) 809#define CyRDCR (0x0E*2) 810#define CySCHR1 (0x1A*2) 811#define CySCHR2 (0x1B*2) 812#define CySCHR3 (0x1C*2) 813#define CySCHR4 (0x1D*2) 814#define CySCRL (0x22*2) 815#define CySCRH (0x23*2) 816#define CyLNC (0x24*2) 817#define CyMCOR1 (0x15*2) 818#define CyMCOR2 (0x16*2) 819#define CyRTPR (0x21*2) 820#define CyMSVR1 (0x6C*2) 821#define CyMSVR2 (0x6D*2) 822#define CyANY_DELTA (0xF0) 823#define CyDSR (0x80) 824#define CyCTS (0x40) 825#define CyRI (0x20) 826#define CyDCD (0x10) 827#define CyDTR (0x02) 828#define CyRTS (0x01) 829#define CyPVSR (0x6F*2) 830#define CyRBPR (0x78*2) 831#define CyRCOR (0x7C*2) 832#define CyTBPR (0x72*2) 833#define CyTCOR (0x76*2) 834 835/* Custom Registers */ 836 837#define CyPLX_VER (0x3400) 838#define PLX_9050 0x0b 839#define PLX_9060 0x0c 840#define PLX_9080 0x0d 841 842/***************************************************************************/ 843 844#endif /* __KERNEL__ */ 845#endif /* _LINUX_CYCLADES_H */ 846