1/* -*- linux-c -*- */ 2/* 3 * Copyright (C) 2001 By Joachim Martillo, Telford Tools, Inc. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 * 10 **/ 11 12#include <linux/module.h> 13#include <linux/kernel.h> 14#include <linux/pci.h> 15#include <linux/stddef.h> 16#include <linux/string.h> 17#include <linux/sockios.h> 18#include <asm/io.h> 19#include <asm/byteorder.h> 20#include <asm/pgtable.h> 21#include <linux/skbuff.h> 22#include <linux/if_arp.h> 23#include <linux/fs.h> 24#include <linux/sched.h> 25#include <asm/uaccess.h> 26#include <linux/version.h> 27#include <linux/etherdevice.h> 28#include <linux/init.h> 29#include "Reg9050.h" 30#include "8253xctl.h" 31#include "ring.h" 32#include "8253x.h" 33#include "crc32dcl.h" 34#include "8253xmcs.h" 35#include "sp502.h" 36 37/* card names */ 38 39char *aura_functionality[] = 40{ 41 "NR", 42 "AO", 43 "NA", 44 "UN" 45}; 46 47char *board_type[] = 48{ 49 "unknown", 50 "1020P", 51 "1520P", 52 "2020P", 53 "2520P", 54 "4020P", 55 "4520P", 56 "8020P", 57 "8520P", 58 "SUNSE", 59 "WANMS", 60 "1020C", 61 "1520C", 62 "2020C", 63 "2520C", 64 "4020C", 65 "4520C", 66 "8020C", 67 "8520C", 68}; 69 70unsigned int sab8253x_rebootflag = 0; 71 72AURAXX20PARAMS AuraXX20DriverParams; /* loaded at startup */ 73 /* from variables below */ 74SAB_BOARD *AuraBoardRoot = NULL; /* The order of this list is not important */ 75SAB_CHIP *AuraChipRoot = NULL; /* chips grouped by board chip0 before chip1 */ 76SAB_PORT *AuraPortRoot = NULL; /* ports grouped by board and by chip, chip0, chip1, etc */ 77AURA_CIM *AuraCimRoot = NULL; /* only used for deallocating the cim structures, etc */ 78/* CIM stands for Communications Interface Module -- the G.Link logic provided by the Altera parts. */ 79 80/* Arrays of lists of boards of each type on a given interrupt */ 81SAB_BOARD *AuraBoardESCC2IrqRoot[NUMINTS]; 82SAB_BOARD *AuraBoardESCC8IrqRoot[NUMINTS]; 83SAB_BOARD *AuraBoardMCSIrqRoot[NUMINTS]; 84 85unsigned int NumSab8253xPorts = 0; 86 87unsigned BD1020Pcounter = 0; /* keep count of each board */ 88unsigned BD1520Pcounter = 0; /* may change to just keeping count */ 89unsigned BD2020Pcounter = 0; /* of the total number of boards */ 90unsigned BD2520Pcounter = 0; 91unsigned BD4020Pcounter = 0; 92unsigned BD4520Pcounter = 0; 93unsigned BD8020Pcounter = 0; 94unsigned BD8520Pcounter = 0; 95 96unsigned BD1020CPcounter = 0; /* keep count of each board */ 97unsigned BD1520CPcounter = 0; /* may change to just keeping count */ 98unsigned BD2020CPcounter = 0; /* of the total number of boards */ 99unsigned BD2520CPcounter = 0; 100unsigned BD4020CPcounter = 0; 101unsigned BD4520CPcounter = 0; 102unsigned BD8020CPcounter = 0; 103unsigned BD8520CPcounter = 0; 104 105unsigned BDMCScounter = 0; 106 107 108static int auraXX20n_debug = 0; /* turns on lots of */ 109 /* debugging messages*/ 110static char* auraXX20n_name = 0;/* set net dev name on command line */ 111static char *sab8253xc_name = "sab8253xc"; 112static int sab8253xc_major = 0; 113int sab8253xn_listsize = 32; /* recommend descriptor list size */ 114int sab8253xn_rbufsize = RXSIZE; /* recommend rbuf list size */ 115int sab8253xt_listsize = 256; /* recommend descriptor list size */ 116int sab8253xt_rbufsize = 32; /* recommend rbuf list size for tty */ 117int sab8253xs_listsize = 64; /* recommend descriptor list size */ 118int sab8253xs_rbufsize = RXSIZE; /* recommend rbuf list size */ 119int sab8253xc_listsize = 64; /* recommend descriptor list size */ 120int sab8253xc_rbufsize = RXSIZE; /* recommend rbuf list size for tty */ 121int xx20_minorstart = 128; 122int sab8253x_vendor_id = PCI_VENDOR_ID_AURORATECH; 123int sab8253x_cpci_device_id = PCI_DEVICE_ID_AURORATECH_CPCI; 124int sab8253x_wmcs_device_id = PCI_DEVICE_ID_AURORATECH_WANMS; 125int sab8253x_mpac_device_id = PCI_DEVICE_ID_AURORATECH_MULTI; 126int sab8253x_default_sp502_mode = SP502_RS232_MODE; 127 128MODULE_PARM(sab8253x_vendor_id, "i"); 129MODULE_PARM(sab8253x_cpci_device_id, "i"); 130MODULE_PARM(sab8253x_wmcs_device_id, "i"); 131MODULE_PARM(sab8253x_mpac_device_id, "i"); 132MODULE_PARM(sab8253x_default_sp502_mode, "i"); 133 134MODULE_PARM(xx20_minorstart, "i"); 135MODULE_PARM(sab8253xc_major, "i"); 136MODULE_PARM(auraXX20n_debug, "i"); 137MODULE_PARM(auraXX20n_name, "s"); /* this and the following for sync */ 138MODULE_PARM(sab8253xn_listsize, "i"); /* network driver */ 139MODULE_PARM(sab8253xn_rbufsize, "i"); /* network driver */ 140MODULE_PARM(sab8253xt_listsize, "i"); /* tty driver */ 141MODULE_PARM(sab8253xt_rbufsize, "i"); /* tty driver */ 142MODULE_PARM(sab8253xc_listsize, "i"); /* network driver */ 143MODULE_PARM(sab8253xc_rbufsize, "i"); /* network driver */ 144MODULE_PARM(sab8253xs_listsize, "i"); /* tty driver */ 145MODULE_PARM(sab8253xs_rbufsize, "i"); /* tty driver */ 146MODULE_PARM(sab8253xc_name, "s"); 147 148struct pci_dev *XX20lastpdev = NULL; /* just used for finding all PCI devices */ 149static SAB_BOARD *find_ati_multiport_card(void); /* actually implemented */ 150static SAB_BOARD *find_ati_cpci_card(void); /* to be done */ 151static SAB_BOARD *find_ati_wanms_card(void); /* to be done */ 152 153#if (!defined(MODULE)) && (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0)) 154 /* unpleasantness for 2.2 kernels 155 * and probe illogic */ 156 157 /* The LRP project is still working on 158 2.2.* kernels but I suspect 159 that initially we will see more 160 purchases for complete Linux 161 machines using 2.4.*, LRP 162 machines tend to be underpowered 163 and have a paucity of PCI slots 164 */ 165 166unsigned int do_probe = 1; 167#endif 168 169 /* One could argue that these could be in */ 170 /* the 8253xnet.c file but they are fairly */ 171 /* intimately involved with initialization.*/ 172struct net_device *Sab8253xRoot = NULL; 173 174struct net_device auraXX20n_prototype = /* used for the network device */ 175{ 176 "8253x0", 177 0, 0, 0, 0, 178 0x000, 179 -1, /* bad irq */ 180 0, 0, 0, 181 NULL, 182 sab8253xn_init /* network driver initialization */ 183}; 184 185struct file_operations sab8253xc_fops = 186{ 187#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 4, 0)) 188 NULL, 189#endif 190 NULL, /* llseek */ 191 sab8253xc_read, /* read */ 192 sab8253xc_write, /* write */ 193 NULL, /* readdir */ 194 sab8253xc_poll, /* poll */ 195 sab8253xc_ioctl, /* ioctl */ 196 NULL, /* mmap */ 197 sab8253xc_open, /* open */ 198 NULL, /* flush */ 199 sab8253xc_release, /* release */ 200 NULL, /* fsync */ 201 sab8253xc_fasync, /* fasync */ 202 NULL, /* check_media_change */ 203 NULL, /* revalidate */ 204 NULL /* lock */ 205}; 206 207 208/* A few function defined in this file */ 209/* These functions are basically functionality */ 210/* independent -- they are used with asynchronous ttys */ 211/* synchronous ttys, the network device and the */ 212/* raw character device */ 213 214 /* used for reading and writing ports 215 readw and writew require some reprogramming 216 of the PLX9050 217 */ 218static unsigned char aura_readb(struct sab_port *port, unsigned char *reg); 219static unsigned char wmsaura_readb(struct sab_port *port, unsigned char *reg); 220static unsigned short aura_readw(struct sab_port *port, unsigned short *reg); 221static unsigned short wmsaura_readw(struct sab_port *port, unsigned short *reg); 222static void aura_writeb(struct sab_port *port, unsigned char *reg,unsigned char val); 223static void wmsaura_writeb(struct sab_port *port, unsigned char *reg,unsigned char val); 224static void aura_writew(struct sab_port *port, unsigned short *reg,unsigned short val); 225static void wmsaura_writew(struct sab_port *port, unsigned short *reg,unsigned short val); 226 227static void aura_readfifo(struct sab_port *port, unsigned char *buf, unsigned int nbytes); 228static void aura_writefifo(struct sab_port *port); 229 230static void wmsaura_readfifo(struct sab_port *port, unsigned char *buf, unsigned int nbytes); 231static void wmsaura_writefifo(struct sab_port *port); 232 233/* function definitions */ 234 235/* [124]X20 type cards */ 236static void DisableESCC2Interrupts(SAB_CHIP *chipptr) /* in processing ports may have to disable ints */ 237{ 238 struct sab82532_async_wr_regs *regs; 239 240 regs = chipptr->c_regs; 241 writeb(0xff,®s->pim); /* All interrupts off */ 242 /* Note that regs/->c_regs 243 is set to base reg 244 address, thus taking 245 address or regs->pim 246 gets the address of 247 the PIM register/int mask */ 248} 249 250static SAB_CHIP* CreateESCC2(SAB_BOARD *bptr, unsigned int offset) 251{ 252 SAB_CHIP *cptr; 253 struct sab82532_async_wr_regs *regs; 254 255 printk(KERN_ALERT 256 "auraXX20n: creating ESCC2 structure on board %p at offset %x.\n", 257 bptr, offset); 258 259 cptr = (SAB_CHIP*) kmalloc(sizeof(SAB_CHIP), GFP_KERNEL); 260 if(cptr == NULL) 261 { 262 printk(KERN_ALERT 263 "auraXX20n: Failed to create ESCC2 structure on board %p at offset %x.\n", 264 bptr, offset); 265 return NULL; 266 } 267 memset(cptr, 0, sizeof(SAB_CHIP)); 268 cptr->chip_type = ESCC2; 269 cptr->c_board = bptr; 270 cptr->c_cim = NULL; 271 cptr->c_chipno = (offset ? 1 : 0); /* first or second chip on board */ 272 cptr->c_revision = 273 (readb(((char *)bptr->virtbaseaddress2) + offset + SAB85232_REG_VSTR) & 274 SAB82532_VSTR_VN_MASK); 275 cptr->c_nports = 2; 276 cptr->c_portbase = NULL; 277 cptr->next = AuraChipRoot; /* chips are added to chiplist in reverse order */ 278 AuraChipRoot = cptr; 279 cptr->next_by_board = bptr->board_chipbase; /* likewise for the local board chiplist */ 280 bptr->board_chipbase = cptr; 281 printk(KERN_ALERT "auraXX20n: chip %d on board %p is revision %d.\n", 282 cptr->c_chipno, bptr, cptr->c_revision); 283 284 /* lets set up the generic parallel 285 * port register which is used to 286 * control signaling and other stuff*/ 287 /* 288 * SAB82532 (Aurora) 1 8-bit parallel port 289 * To summarize the use of the parallel port: 290 * RS-232 291 * A B I/O descr 292 * P0 P4 output TxClk ctrl 293 * P1 P5 output DTR 294 * P2 P6 input DSR 295 * P3 P7 output 485 control 296 * 297 */ 298 /* 299 * Configuring the parallel port 300 */ 301 302 regs = (struct sab82532_async_wr_regs *)(((char *)bptr->virtbaseaddress2) + offset); 303 304 DEBUGPRINT((KERN_ALERT "Writing 0x44 to 0x%p + 0x%x for chip %d\n", 305 regs, SAB82532_REG_PCR, cptr->c_chipno)); 306 307 writeb(0x44,®s->pcr); /* 2 input bits */ 308 writeb(0xff,®s->pim);/* All interrupts off */ 309 writeb(0x33,®s->pvr); /* Txclk and DTR low */ 310 311 cptr->c_regs = (void*) regs; 312 cptr->int_disable = DisableESCC2Interrupts; 313 return cptr; 314} 315 316static void CreateESCC2Port(SAB_CHIP *cptr, unsigned int portno, unsigned int function) 317{ 318 SAB_BOARD *bptr; 319 SAB_PORT *pptr; 320 extern void sab8253x_setup_ttyport(struct sab_port *p_port) ; 321 322 ++NumSab8253xPorts; 323 bptr = cptr->c_board; 324 pptr = (SAB_PORT*) kmalloc(sizeof(SAB_PORT), GFP_KERNEL); 325 if(pptr == NULL) 326 { 327 printk(KERN_ALERT 328 "auraXX20n: Failed to create ESCC2 port structure on chip %p on board %p.\n", 329 cptr, bptr); 330 return; 331 } 332 memset(pptr, 0, sizeof(SAB_PORT)); 333 DEBUGPRINT 334 ((KERN_ALERT "Setting up port %d, chipno %d for %s type board number %d.\n", 335 portno, cptr->c_chipno, board_type[bptr->b_type],bptr->board_number)); 336 pptr->portno = portno; 337 pptr->chip=cptr; 338 pptr->board=bptr; 339 pptr->open_type=OPEN_NOT; 340 pptr->is_console=0; 341 pptr->regs= 342 (union sab82532_regs *) 343 (((unsigned int)cptr->c_regs) + 344 (portno * SAB82532_REG_SIZE)); 345 pptr->type = cptr->c_revision; 346 pptr->function = function; 347 348 /* Simpify reading */ 349#define PVR pptr->regs->async_write.pvr 350#define PCR pptr->regs->async_write.pcr 351#define PIM pptr->regs->async_write.pim 352#define ISR0 pptr->regs->async_read.isr0 353#define IMR0 pptr->regs->async_write.imr0 354#define IMR1 pptr->regs->async_write.imr1 355#define PIS pptr->regs->async_read.pis 356#define VSTR pptr->regs->async_read.vstr 357#define STAR pptr->regs->async_read.star 358#define MODE pptr->regs->async_read.mode 359 360 pptr->irq = bptr->b_irq; 361 if(portno == 0) 362 { /* Port A .... */ 363 pptr->dsr.reg=(unsigned char *)&(PVR); 364 pptr->dsr.mask=0x04; 365 pptr->dsr.irq=PIS_IDX; 366 pptr->dsr.irqmask=0x04; 367 368 pptr->dtr.reg=(unsigned char *)&(PVR); 369 pptr->dtr.mask=0x02; 370 371 pptr->txclkdir.reg=(unsigned char *)&(PVR); 372 pptr->txclkdir.mask=0x01; 373 } 374 else 375 { /* Port B */ 376 pptr->dsr.reg=(unsigned char *)&(PVR); 377 pptr->dsr.mask=0x40; 378 pptr->dsr.irq=PIS_IDX; 379 pptr->dsr.irqmask=0x40; 380 381 pptr->dtr.reg=(unsigned char *)&(PVR); 382 pptr->dtr.mask=0x20; 383 384 pptr->txclkdir.reg=(unsigned char *)&(PVR); 385 pptr->txclkdir.mask=0x10; 386 } 387 pptr->dsr.inverted=1; 388 pptr->dsr.cnst = 0; 389 pptr->dtr.inverted=1; 390 pptr->dtr.cnst = 0; 391 pptr->txclkdir.inverted=1; 392 393 pptr ->dcd.reg =(unsigned char *) &(VSTR); 394 395 DEBUGPRINT((KERN_ALERT "cd register set to 0x%p\n", pptr ->dcd.reg)); 396 397 pptr->dcd.mask = SAB82532_VSTR_CD; 398 pptr->dcd.inverted = 1; 399 pptr->dcd.irq=ISR0_IDX; 400 pptr->dcd.irqmask=SAB82532_ISR0_CDSC; 401 pptr->dcd.cnst = 0; 402 403 pptr->cts.reg = (unsigned char *)&(STAR); 404 pptr->cts.mask = SAB82532_STAR_CTS; 405 pptr->cts.inverted = 0; 406 pptr->cts.irq=ISR1_IDX; 407 pptr->cts.irqmask=SAB82532_ISR1_CSC; 408 pptr->cts.cnst = 0; 409 410 pptr->rts.reg = (unsigned char *)&(MODE); 411 pptr->rts.mask = SAB82532_MODE_FRTS; 412 pptr->rts.inverted = 1; 413 pptr->rts.cnst = SAB82532_MODE_RTS; 414 415 416 /* Set the read and write function */ 417 pptr->readbyte=aura_readb; 418 pptr->readword=aura_readw; 419 pptr->writebyte=aura_writeb; 420 pptr->writeword=aura_writew; 421 pptr->readfifo=aura_readfifo; 422 pptr->writefifo=aura_writefifo; 423 424 sab8253x_setup_ttyport(pptr); /* asynchronous */ 425 /* ttys are default, basic */ 426 /* initialization, everything */ 427 /* else works as a modification */ 428 /* thereof */ 429 430 pptr->next = AuraPortRoot; 431 AuraPortRoot = pptr; 432 pptr->next_by_chip = cptr->c_portbase; 433 cptr->c_portbase = pptr; 434 pptr->next_by_board = bptr->board_portbase; 435 bptr->board_portbase = pptr; 436} 437 438/* 8x20 type functions */ 439 440static void DisableESCC8Interrupts(SAB_CHIP *chipptr) 441{ 442 unsigned int regbase; /* a lot more to do for ESCC8 */ 443 444 regbase = (unsigned int) chipptr->c_regs; 445 writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_A); /* All interrupts off */ 446 writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_B); /* All interrupts off */ 447 writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_C); /* All interrupts off */ 448 writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_D); /* All interrupts off */ 449} 450 451static SAB_CHIP* CreateESCC8(SAB_BOARD *bptr, unsigned int offset) 452{ 453 SAB_CHIP *cptr; 454 unsigned int regbase; 455 456 printk(KERN_ALERT 457 "auraXX20n: creating ESCC8 structure on board %p at offset %x.\n", 458 bptr, offset); 459 460 cptr = (SAB_CHIP*) kmalloc(sizeof(SAB_CHIP), GFP_KERNEL); 461 if(cptr == NULL) 462 { 463 printk(KERN_ALERT 464 "auraXX20n: Failed to create ESCC8 structure on board %p at offset %x.\n", 465 bptr, offset); 466 return NULL; 467 } 468 memset(cptr, 0, sizeof(SAB_CHIP)); 469 cptr->chip_type = ESCC8; 470 cptr->c_board = bptr; 471 cptr->c_cim = NULL; 472 cptr->c_chipno = (offset ? 1 : 0); /* no card actually has 2 ESCC8s on it */ 473 cptr->c_revision = 474 (readb(((char *)bptr->virtbaseaddress2) + offset + SAB85232_REG_VSTR) & 475 SAB82532_VSTR_VN_MASK); 476 cptr->c_nports = 8; 477 cptr->c_portbase = NULL; /* used for the list of ports associated 478 with this chip 479 */ 480 cptr->next = AuraChipRoot; 481 AuraChipRoot = cptr; 482 cptr->next_by_board = bptr->board_chipbase; 483 bptr->board_chipbase = cptr; 484 printk(KERN_ALERT "auraXX20n: chip %d on board %p is revision %d.\n", 485 cptr->c_chipno, bptr, cptr->c_revision); 486 487 /* lets set up the generic parallel 488 * port register which is used to 489 * control signaling and other stuff*/ 490 491 /* SAB82538 4 8-bits parallel ports 492 * To summarize the use of the parallel port: 493 * RS-232 494 * Parallel port A -- TxClkdir control (output) ports 0 - 7 495 * Parallel port B -- DTR (output) ports 0 - 7 496 * Parallel port C -- DSR (input) ports 0 - 7 497 * Parallel port D -- driver power down (output) drivers 0 - 3 498 * 499 * Note port D is not used on recent boards 500 */ 501 502 regbase = (unsigned int)(((char *)bptr->virtbaseaddress2) + offset); 503 504 DEBUGPRINT((KERN_ALERT "Setting up parallel port A (0x%x), 0x%x, 0x%x, 0x%x\n", regbase, 505 SAB82538_REG_PCR_A, SAB82538_REG_PIM_A, SAB82538_REG_PVR_A)); 506 507 /* Configuring Parallel Port A (Clkdir)*/ 508 writeb(0x0,((unsigned char *)regbase) + SAB82538_REG_PCR_A); /* All output bits */ 509 writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_A); /* All interrupts off */ 510 writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PVR_A); /* All low */ 511 512 DEBUGPRINT((KERN_ALERT "Setting up parallel port B (0x%x), 0x%x, 0x%x, 0x%x\n", regbase, 513 SAB82538_REG_PCR_B,SAB82538_REG_PIM_B,SAB82538_REG_PVR_B)); 514 515 writeb(0x0,((unsigned char *)regbase) + SAB82538_REG_PCR_B); /* All output bits */ 516 writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_B); /* All interrupts off */ 517 writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PVR_B); /* All low */ 518 519 DEBUGPRINT((KERN_ALERT "Setting up parallel port C (0x%x), 0x%x, 0x%x, 0x%x\n", regbase, 520 SAB82538_REG_PCR_C, SAB82538_REG_PIM_C, SAB82538_REG_PVR_C)); 521 522 writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PCR_C); /* All intput bits */ 523 writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_C); /* All interrupts off */ 524 /* don't set port value register on input register */ 525 526 /* Configuring Parallel Port D */ 527 528 DEBUGPRINT((KERN_ALERT "Setting up parallel port D (0x%x), 0x%x, 0x%x, 0x%x\n", regbase, 529 SAB82538_REG_PCR_D, SAB82538_REG_PIM_D, SAB82538_REG_PVR_D)); 530 writeb(0x0f,((unsigned char *)regbase) + SAB82538_REG_PCR_D); /* 4 input bits */ 531 writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_D); /* All interrupts off */ 532 /* don't set port value register on input register */ 533 534 /* The priority rotation thing */ 535 536 DEBUGPRINT((KERN_ALERT "Setting IVA (0x%x + 0x%x = 0x%x\n", regbase, 537 SAB82532_REG_IVA, regbase + SAB82532_REG_IVA)); 538 539 writeb(SAB82538_IVA_ROT, ((unsigned char *)regbase) + SAB82532_REG_IVA); 540 541 cptr->c_regs = (void*) regbase; 542 cptr->int_disable = DisableESCC8Interrupts; 543 return cptr; 544} 545 546static void DisableESCC8InterruptsFromCIM(SAB_CHIP *chipptr) 547{ 548 unsigned int regbase; /* a lot more to do for ESCC8 */ 549 550 regbase = (unsigned int) chipptr->c_regs; 551 writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_A)); /* All interrupts off */ 552 writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_B)); /* All interrupts off */ 553 writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_C)); /* All interrupts off */ 554 writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_D)); /* All interrupts off */ 555} 556 557static void CreateESCC8Port(SAB_CHIP *cptr, unsigned int portno, unsigned int function) 558{ 559 SAB_BOARD *bptr; 560 SAB_PORT *pptr; 561 extern void sab8253x_setup_ttyport(struct sab_port *p_port) ; 562 563 ++NumSab8253xPorts; 564 bptr = cptr->c_board; 565 pptr = (SAB_PORT*) kmalloc(sizeof(SAB_PORT), GFP_KERNEL); 566 if(pptr == NULL) 567 { 568 printk(KERN_ALERT 569 "auraXX20n: Failed to create ESCC2 port structure on chip %p on board %p.\n", 570 cptr, bptr); 571 return; 572 } 573 memset(pptr, 0, sizeof(SAB_PORT)); 574 DEBUGPRINT 575 ((KERN_ALERT "Setting up port %d, chipno %d for %s type board number %d.\n", 576 portno, cptr->c_chipno, board_type[bptr->b_type],bptr->board_number)); 577 pptr->portno = portno; 578 pptr->chip=cptr; 579 pptr->board=bptr; 580 pptr->open_type=OPEN_NOT; 581 pptr->is_console=0; 582 pptr->regs= 583 (union sab82532_regs *) 584 (((unsigned int)cptr->c_regs) + 585 (portno * SAB82538_REG_SIZE)); 586 pptr->type = cptr->c_revision; 587 pptr->function = function; 588 589 pptr->irq = bptr->b_irq; 590 591 pptr->dsr.reg = ((unsigned char *)cptr->c_regs) + SAB82538_REG_PVR_C; 592 pptr->dsr.mask = 0x1 << portno; 593 pptr->dsr.inverted = 1; 594 pptr->dsr.irq=PIS_IDX; /* need to check this constant */ 595 pptr->dsr.irqmask=0x1 << portno; 596 pptr->dsr.cnst = 0; 597 598 pptr->txclkdir.reg = ((unsigned char *)cptr->c_regs) + SAB82538_REG_PVR_A; 599 pptr->txclkdir.mask = 0x1 << portno; 600 /* NOTE: Early 8 ports boards had different tx clkdir sense */ 601 pptr->txclkdir.inverted = 1; 602 603 pptr->dtr.reg = ((unsigned char *)cptr->c_regs) + SAB82538_REG_PVR_B; 604 pptr->dtr.mask = 0x1 << portno; 605 pptr->dtr.inverted = 1; 606 pptr->dtr.cnst = 0; 607 608 pptr ->dcd.reg = (unsigned char *)&(VSTR); 609 610 DEBUGPRINT((KERN_ALERT "cd register set to 0x%p\n", pptr ->dcd.reg)); 611 612 pptr->dcd.mask = SAB82532_VSTR_CD; 613 pptr->dcd.inverted = 1; 614 pptr->dcd.irq=ISR0_IDX; 615 pptr->dcd.irqmask=SAB82532_ISR0_CDSC; 616 pptr->dcd.cnst = 0; 617 618 pptr->cts.reg = (unsigned char *)&(STAR); 619 pptr->cts.mask = SAB82532_STAR_CTS; 620 pptr->cts.inverted = 0; 621 pptr->cts.irq=ISR1_IDX; 622 pptr->cts.irqmask=SAB82532_ISR1_CSC; 623 pptr->cts.cnst = 0; 624 625 pptr->rts.reg = (unsigned char *)&(MODE); 626 pptr->rts.mask = SAB82532_MODE_FRTS; 627 pptr->rts.inverted = 1; 628 pptr->rts.cnst = SAB82532_MODE_RTS; 629 630 631 /* Set the read and write function */ 632 pptr->readbyte=aura_readb; 633 pptr->readword=aura_readw; 634 pptr->writebyte=aura_writeb; 635 pptr->writeword=aura_writew; 636 pptr->readfifo=aura_readfifo; 637 pptr->writefifo=aura_writefifo; 638 639 sab8253x_setup_ttyport(pptr); /* asynchronous */ 640 /* ttys are default, basic */ 641 /* initialization, everything */ 642 /* else works as a modification */ 643 /* thereof */ 644 645 pptr->next = AuraPortRoot; 646 AuraPortRoot = pptr; 647 pptr->next_by_chip = cptr->c_portbase; 648 cptr->c_portbase = pptr; 649 pptr->next_by_board = bptr->board_portbase; 650 bptr->board_portbase = pptr; 651} 652 653/* Multichannel server functions */ 654 655static SAB_CHIP* CreateESCC8fromCIM(SAB_BOARD *bptr, AURA_CIM *cim, unsigned int chipno) 656{ 657 SAB_CHIP *cptr; 658 unsigned int regbase; 659 660 printk(KERN_ALERT 661 "auraXX20n: creating ESCC8 %d structure on board %p from cim %p.\n", 662 chipno, bptr, cim); 663 664 cptr = (SAB_CHIP*) kmalloc(sizeof(SAB_CHIP), GFP_KERNEL); 665 if(cptr == NULL) 666 { 667 printk(KERN_ALERT 668 "auraXX20n: Failed to create ESCC8 structure %d on board %p at from cim %p.\n", 669 chipno, bptr, cim); 670 return NULL; 671 } 672 673 memset(cptr, 0, sizeof(SAB_CHIP)); 674 cptr->chip_type = ESCC8; 675 cptr->c_board = bptr; 676 cptr->c_cim = cim; 677 cptr->c_chipno = chipno; 678 cptr->c_revision = 679 (readb((unsigned char *) (bptr->CIMCMD_REG + 680 (CIMCMD_RDREGB | (((chipno*8) << 6) | SAB85232_REG_VSTR)))) 681 & SAB82532_VSTR_VN_MASK); 682 cptr->c_nports = 8; 683 cptr->c_portbase = NULL; /* used for the list of ports associated 684 with this chip 685 */ 686 cptr->next = AuraChipRoot; 687 AuraChipRoot = cptr; 688 cptr->next_by_board = bptr->board_chipbase; 689 bptr->board_chipbase = cptr; 690 691 cptr->next_by_cim = cim->ci_chipbase; 692 cim->ci_chipbase = cptr; 693 694 printk(KERN_ALERT "auraXX20n: chip %d on board %p is revision %d.\n", 695 cptr->c_chipno, bptr, cptr->c_revision); 696 697 /* lets set up the generic parallel 698 * port register which is used to 699 * control signaling and other stuff*/ 700 701 /* SAB82538 4 8-bits parallel ports 702 * To summarize the use of the parallel port: 703 * RS-232 704 * Parallel port A -- TxClkdir control (output) ports 0 - 7 705 * Parallel port B -- DTR (output) ports 0 - 7 706 * Parallel port C -- DSR (input) ports 0 - 7 707 * Parallel port D -- driver power down (output) drivers 0 - 3 708 * 709 * Note port D is not used on recent boards 710 */ 711 712 regbase = (unsigned int) 713 (bptr->CIMCMD_REG + (0 | (((chipno*8) << 6) | 0))); /* need to add in RDB/WRB cmd bits 714 * and reg offset (> 32) */ 715 716 DEBUGPRINT((KERN_ALERT "Setting up parallel port A (0x%x), 0x%x, 0x%x, 0x%x\n", regbase, 717 SAB82538_REG_PCR_A, SAB82538_REG_PIM_A, SAB82538_REG_PVR_A)); 718 719 /* Configuring Parallel Port A (Clkdir)*/ 720 writeb(0x00,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PCR_A)); /* All output bits */ 721 writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_A)); /* All interrupts off */ 722 writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PVR_A)); /* All low */ 723 724 DEBUGPRINT((KERN_ALERT "Setting up parallel port B (0x%x), 0x%x, 0x%x, 0x%x\n", regbase, 725 SAB82538_REG_PCR_B,SAB82538_REG_PIM_B,SAB82538_REG_PVR_B)); 726 727 writeb(0x00,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PCR_B)); /* All output bits */ 728 writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_B)); /* All interrupts off */ 729 writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PVR_B)); /* All low */ 730 731 DEBUGPRINT((KERN_ALERT "Setting up parallel port C (0x%x), 0x%x, 0x%x, 0x%x\n", regbase, 732 SAB82538_REG_PCR_C, SAB82538_REG_PIM_C, SAB82538_REG_PVR_C)); 733 734 writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PCR_C)); /* All intput bits */ 735 writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_C)); /* All interrupts off */ 736 /* don't set port value register on input register */ 737 738 /* Configuring Parallel Port D */ 739 740 DEBUGPRINT((KERN_ALERT "Setting up parallel port D (0x%x), 0x%x, 0x%x, 0x%x\n", regbase, 741 SAB82538_REG_PCR_D, SAB82538_REG_PIM_D, SAB82538_REG_PVR_D)); 742 writeb(0x0f,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PCR_D)); /* 4 input bits */ 743 writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_D)); /* All interrupts off */ 744 /* don't set port value register on input register */ 745 746 /* The priority rotation thing */ 747 748 DEBUGPRINT((KERN_ALERT "Setting IVA (0x%x + 0x%x = 0x%x\n", regbase, 749 SAB82532_REG_IVA, regbase + SAB82532_REG_IVA)); 750 751 writeb(SAB82538_IVA_ROT, ((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82532_REG_IVA)); 752 writeb(0, ((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82532_REG_IPC)); 753 754 cptr->c_regs = (void*) regbase; 755 cptr->int_disable = DisableESCC8InterruptsFromCIM; 756 return cptr; 757} 758 759static void CreateESCC8PortWithCIM(SAB_CHIP *cptr, unsigned int portno, 760 AURA_CIM *cim, unsigned flag) 761{ 762 SAB_BOARD *bptr; 763 SAB_PORT *pptr; 764 extern void sab8253x_setup_ttyport(struct sab_port *p_port) ; 765 766 ++NumSab8253xPorts; 767 bptr = cptr->c_board; 768 pptr = (SAB_PORT*) kmalloc(sizeof(SAB_PORT), GFP_KERNEL); 769 if(pptr == NULL) 770 { 771 printk(KERN_ALERT 772 "auraXX20n: Failed to create ESCC2 port structure on chip %p on board %p.\n", 773 cptr, bptr); 774 return; 775 } 776 memset(pptr, 0, sizeof(SAB_PORT)); 777 DEBUGPRINT 778 ((KERN_ALERT "Setting up port %d, chipno %d for %s type board number %d.\n", 779 portno, cptr->c_chipno, board_type[bptr->b_type],bptr->board_number)); 780 pptr->portno = portno; 781 pptr->chip=cptr; 782 pptr->board=bptr; 783 pptr->open_type=OPEN_NOT; 784 pptr->is_console=0; 785 pptr->regs= 786 (union sab82532_regs *) 787 (((unsigned int)cptr->c_regs) + 788 (portno << 6)); /* addressing is different when there is a cim */ 789 pptr->type = cptr->c_revision; 790 pptr->function = (((cim->ci_flags & CIM_SYNC) || flag) ? FUNCTION_NR : 791 FUNCTION_AO); 792 793 pptr->irq = bptr->b_irq; 794 795 pptr->dsr.reg = ((unsigned char *)cptr->c_regs) + SAB82538_REG_PVR_C; 796 pptr->dsr.mask = 0x1 << portno; 797 pptr->dsr.inverted = 1; 798 pptr->dsr.irq=PIS_IDX; /* need to check this constant */ 799 pptr->dsr.irqmask=0x1 << portno; 800 pptr->dsr.cnst = 0; 801 802 pptr->txclkdir.reg = ((unsigned char *)cptr->c_regs) + SAB82538_REG_PVR_A; 803 pptr->txclkdir.mask = 0x1 << portno; 804 /* NOTE: Early 8 ports boards had different tx clkdir sense */ 805 pptr->txclkdir.inverted = 1; 806 807 pptr->dtr.reg = ((unsigned char *)cptr->c_regs) + SAB82538_REG_PVR_B; 808 pptr->dtr.mask = 0x1 << portno; 809 pptr->dtr.inverted = 1; 810 pptr->dtr.cnst = 0; 811 812 pptr->dcd.reg = ((unsigned char *)pptr->regs) + SAB85232_REG_VSTR; 813 814 DEBUGPRINT((KERN_ALERT "cd register set to 0x%p\n", pptr->dcd.reg)); 815 816 pptr->dcd.mask = SAB82532_VSTR_CD; 817 pptr->dcd.inverted = 1; 818 pptr->dcd.irq=ISR0_IDX; 819 pptr->dcd.irqmask=SAB82532_ISR0_CDSC; 820 pptr->dcd.cnst = 0; 821 822 pptr->cts.reg = (unsigned char *)&(STAR); 823 pptr->cts.mask = SAB82532_STAR_CTS; 824 pptr->cts.inverted = 0; 825 pptr->cts.irq=ISR1_IDX; 826 pptr->cts.irqmask=SAB82532_ISR1_CSC; 827 pptr->cts.cnst = 0; 828 829 pptr->rts.reg = (unsigned char *)&(MODE); 830 pptr->rts.mask = SAB82532_MODE_FRTS; 831 pptr->rts.inverted = 1; 832 pptr->rts.cnst = SAB82532_MODE_RTS; 833 834 835 /* Set the read and write function */ 836 pptr->readbyte=wmsaura_readb; 837 pptr->readword=wmsaura_readw; 838 pptr->writebyte=wmsaura_writeb; 839 pptr->writeword=wmsaura_writew; 840 pptr->readfifo=wmsaura_readfifo; 841 pptr->writefifo=wmsaura_writefifo; 842 843 sab8253x_setup_ttyport(pptr); /* asynchronous */ 844 /* ttys are default, basic */ 845 /* initialization, everything */ 846 /* else works as a modification */ 847 /* thereof */ 848 849 pptr->next = AuraPortRoot; 850 AuraPortRoot = pptr; 851 852 pptr->next_by_chip = cptr->c_portbase; 853 cptr->c_portbase = pptr; 854 855 pptr->next_by_board = bptr->board_portbase; 856 bptr->board_portbase = pptr; 857 858 pptr->next_by_cim = cim->ci_portbase; 859 cim->ci_portbase = pptr; 860} 861 862static void CreateCIMs(SAB_BOARD *bptr) 863{ 864 unsigned int cimnum; 865 unsigned char *wrcsr; 866 unsigned char *rdcsr; 867 unsigned char tmp; 868 AURA_CIM *cim; 869 unsigned short intrmask; 870 871 for(intrmask = 0, cimnum = 0; cimnum < MAX_NCIMS; ++cimnum) 872 { 873 intrmask >>= 2; 874 875 /* 876 * The hardware is mapped. Try writing to CIM CSR. 877 */ 878 wrcsr = bptr->CIMCMD_REG + 879 (CIMCMD_WRCIMCSR | (cimnum << CIMCMD_CIMSHIFT)); 880 rdcsr = bptr->CIMCMD_REG + 881 (CIMCMD_RDCIMCSR | (cimnum << CIMCMD_CIMSHIFT)); 882 883 /* Try to write an 0xff */ 884 writeb((unsigned char) 0xff, (unsigned char *) wrcsr); 885 /* and read it back */ 886 tmp = (unsigned char) readb((unsigned char *) rdcsr); 887 DEBUGPRINT((KERN_ALERT 888 "aura wan mcs: wrcsr %p rdcsr %p cim %d 0xff readback: 0x%x.\n", 889 (void*) wrcsr, (void*) rdcsr, cimnum, tmp)); 890 891 /* make sure it's really all ones. */ 892 if ((tmp & CIMCMD_CIMCSR_TESTMASK) != CIMCMD_CIMCSR_TESTMASK) 893 { 894 printk(KERN_ALERT 895 "aura wan mcs: not found -- wrcsr %p rdcsr %p cim %d 0xff readback: 0x%x.\n", 896 (void*) wrcsr, (void*) rdcsr, cimnum, tmp); 897 continue; 898 } 899 900 /* Try to write a zero */ 901 writeb((unsigned char) 0, (unsigned char*) wrcsr); 902 /* and read it back */ 903 tmp = (unsigned char) readb((unsigned char *) rdcsr); 904 DEBUGPRINT((KERN_ALERT 905 "aura wan mcs: wrcsr %p rdcsr %p cim %d 0x0 readback: 0x%x.\n", 906 (void*) wrcsr, (void*) rdcsr, cimnum, tmp)); 907 908 /* make sure it's really zero. */ 909 if ((tmp & CIMCMD_CIMCSR_TESTMASK) != 0) 910 { 911 printk(KERN_ALERT 912 "aura wan mcs: not found -- wrcsr %p rdcsr %p cim %d 0x0 readback: 0x%x.\n", 913 (void*) wrcsr, (void*) rdcsr, cimnum, tmp); 914 continue; 915 } 916 cim = (AURA_CIM*) kmalloc(sizeof(AURA_CIM), GFP_KERNEL); 917 if(cim == NULL) 918 { 919 printk(KERN_ALERT 920 "aura wan mcs: unable to allocate memory, board %p, cim %d.\n", 921 bptr, cimnum); 922 continue; 923 } 924 cim->ci_num = cimnum; 925 cim->ci_board = bptr; 926 cim->ci_chipbase = NULL; 927 cim->ci_portbase = NULL; 928 cim->ci_nports = CIM_NPORTS; 929 cim->ci_port0lbl = cimnum * CIM_NPORTS; 930 if (mcs_ciminit(bptr, cim) == FALSE) 931 { 932 kfree(cim); 933 continue; 934 } 935 intrmask |= 0xc0; /* turn on the high two bits 936 * a little obscure, borrowed 937 * from solaris driver 0th cim 938 * gets lowest two bits*/ 939 cim->next = AuraCimRoot; 940 AuraCimRoot = cim; 941 cim->next_by_mcs = bptr->b_cimbase; 942 bptr->b_cimbase = cim; 943 printk(KERN_ALERT 944 "aura wan mcs: Created cim %d type %d on board %p.\n", 945 cim->ci_num, cim->ci_type, bptr); 946 } 947 bptr->b_intrmask = intrmask; 948} 949 950/* put the chips on the boards */ 951 952static void SetupAllChips(SAB_BOARD *bptr) 953{ /* note that port ordering */ 954 /* is important in chip setup */ 955 /* the open routine walks the */ 956 /* port list for sync and async */ 957 /* ttys */ 958 SAB_CHIP *chip; 959 AURA_CIM *cim; 960 unsigned int chipno; 961 962 switch(bptr->b_type) 963 { 964 case BD_1020P: 965 case BD_1020CP: 966 /* setup 1 ESCC2 */ 967 chip = CreateESCC2(bptr, 0); 968 if(chip != NULL) 969 { 970 CreateESCC2Port(chip, 1, FUNCTION_NA); 971 CreateESCC2Port(chip, 0, FUNCTION_AO); 972 } 973 974 break; 975 case BD_1520P: 976 case BD_1520CP: 977 /* setup 1 ESCC2 */ 978 chip = CreateESCC2(bptr, 0); 979 if(chip != NULL) 980 { 981 CreateESCC2Port(chip, 1, FUNCTION_NA); 982 CreateESCC2Port(chip, 0, FUNCTION_NR); 983 } 984 break; 985 case BD_2020P: 986 case BD_2020CP: 987 /* setup 1 ESCC2 */ 988 chip = CreateESCC2(bptr, 0); 989 if(chip != NULL) 990 { 991 CreateESCC2Port(chip, 1, FUNCTION_AO); 992 CreateESCC2Port(chip, 0, FUNCTION_AO); 993 } 994 break; 995 case BD_2520P: 996 case BD_2520CP: 997 /* setup 1 ESCC2 */ 998 chip = CreateESCC2(bptr, 0); 999 if(chip != NULL) 1000 { 1001 CreateESCC2Port(chip, 1, FUNCTION_NR); 1002 CreateESCC2Port(chip, 0, FUNCTION_NR); 1003 } 1004 break; 1005 case BD_4020P: 1006 case BD_4020CP: /* do chips in reverCse 1007 order so that they 1008 are on lists in forward 1009 order 1010 */ 1011 /* setup 2 ESCC2 */ 1012 chip = CreateESCC2(bptr, AURORA_4X20_CHIP_OFFSET); 1013 if(chip != NULL) 1014 { 1015 CreateESCC2Port(chip, 1, FUNCTION_AO); 1016 CreateESCC2Port(chip, 0, FUNCTION_AO); 1017 } 1018 chip = CreateESCC2(bptr, 0); 1019 if(chip != NULL) 1020 { 1021 CreateESCC2Port(chip, 1, FUNCTION_AO); 1022 CreateESCC2Port(chip, 0, FUNCTION_AO); 1023 } 1024 break; 1025 case BD_4520P: 1026 case BD_4520CP: 1027 /* setup 2 ESCC2 */ 1028 chip = CreateESCC2(bptr, AURORA_4X20_CHIP_OFFSET); 1029 if(chip != NULL) 1030 { 1031 CreateESCC2Port(chip, 1, FUNCTION_NR); 1032 CreateESCC2Port(chip, 0, FUNCTION_NR); 1033 } 1034 chip = CreateESCC2(bptr, 0); 1035 if(chip != NULL) 1036 { 1037 CreateESCC2Port(chip, 1, FUNCTION_NR); 1038 CreateESCC2Port(chip, 0, FUNCTION_NR); 1039 } 1040 break; 1041 case BD_8020P: 1042 case BD_8020CP: 1043 /* setup 1 ESCC8 */ 1044 chip = CreateESCC8(bptr, 0); 1045 if(chip != NULL) 1046 { 1047 CreateESCC8Port(chip, 7, FUNCTION_AO); 1048 CreateESCC8Port(chip, 6, FUNCTION_AO); 1049 CreateESCC8Port(chip, 5, FUNCTION_AO); 1050 CreateESCC8Port(chip, 4, FUNCTION_AO); 1051 CreateESCC8Port(chip, 3, FUNCTION_AO); 1052 CreateESCC8Port(chip, 2, FUNCTION_AO); 1053 CreateESCC8Port(chip, 1, FUNCTION_AO); 1054 CreateESCC8Port(chip, 0, FUNCTION_AO); 1055 } 1056 break; 1057 case BD_8520P: 1058 case BD_8520CP: 1059 /* setup 1 ESCC8 */ 1060 chip = CreateESCC8(bptr, 0); 1061 if(chip != NULL) 1062 { 1063 CreateESCC8Port(chip, 7, FUNCTION_NR); 1064 CreateESCC8Port(chip, 6, FUNCTION_NR); 1065 CreateESCC8Port(chip, 5, FUNCTION_NR); 1066 CreateESCC8Port(chip, 4, FUNCTION_NR); 1067 CreateESCC8Port(chip, 3, FUNCTION_NR); 1068 CreateESCC8Port(chip, 2, FUNCTION_NR); 1069 CreateESCC8Port(chip, 1, FUNCTION_NR); 1070 CreateESCC8Port(chip, 0, FUNCTION_NR); 1071 } 1072 break; 1073 1074 case BD_WANMCS: 1075 CreateCIMs(bptr); 1076 for(chipno = 7, cim = bptr->b_cimbase; 1077 cim != NULL; cim = cim->next_by_mcs) 1078 { 1079 chip = CreateESCC8fromCIM(bptr, cim, chipno--); 1080 if(chip != NULL) 1081 { 1082 CreateESCC8PortWithCIM(chip, 7, cim, 0); 1083 CreateESCC8PortWithCIM(chip, 6, cim, 0); 1084 CreateESCC8PortWithCIM(chip, 5, cim, 0); 1085 CreateESCC8PortWithCIM(chip, 4, cim, 0); 1086 CreateESCC8PortWithCIM(chip, 3, cim, 0); 1087 CreateESCC8PortWithCIM(chip, 2, cim, 0); 1088 CreateESCC8PortWithCIM(chip, 1, cim, 0); 1089 CreateESCC8PortWithCIM(chip, 0, cim, 0); 1090 } 1091 chip = CreateESCC8fromCIM(bptr, cim, chipno--); 1092 if(chip != NULL) 1093 { 1094 CreateESCC8PortWithCIM(chip, 7, cim, 0); 1095 CreateESCC8PortWithCIM(chip, 6, cim, 0); 1096 CreateESCC8PortWithCIM(chip, 5, cim, 0); 1097 CreateESCC8PortWithCIM(chip, 4, cim, 0); 1098 CreateESCC8PortWithCIM(chip, 3, cim, 0); 1099 CreateESCC8PortWithCIM(chip, 2, cim, 0); 1100 CreateESCC8PortWithCIM(chip, 1, cim, 0); 1101 CreateESCC8PortWithCIM(chip, 0, cim, 1); 1102 } 1103 } 1104 break; 1105 1106 default: 1107 printk(KERN_ALERT "auraXX20n: unable to set up chip for board %p.\n", bptr); 1108 break; 1109 } 1110} 1111 1112/* finding the cards by PCI device type */ 1113 1114static SAB_BOARD* find_ati_cpci_card(void) 1115{ 1116 struct pci_dev *pdev; 1117 unsigned char bus; 1118 unsigned char devfn; 1119 unsigned char pci_latency; 1120 unsigned short pci_command; 1121 SAB_BOARD *bptr; 1122 unsigned control; 1123 unsigned does_sync; 1124 unsigned use_1port; 1125 1126 printk(KERN_ALERT "auraXX20n: finding ati cpci cards.\n"); 1127 1128 bptr = (SAB_BOARD*)kmalloc(sizeof(SAB_BOARD), GFP_KERNEL); 1129 if(bptr == NULL) 1130 { 1131 printk(KERN_ALERT "auraXX20n: could not allocate board memory!\n"); 1132 return 0; 1133 } 1134 memset(bptr, 0, sizeof(SAB_BOARD)); 1135 1136 if(!pcibios_present()) 1137 { 1138 printk(KERN_ALERT "auraXX20n: system does not support PCI bus.\n"); 1139 kfree(bptr); 1140 return 0; 1141 } 1142 DEBUGPRINT((KERN_ALERT "auraXX20n: System supports PCI bus.\n")); 1143 1144 CPCIRESTART: 1145 if(pdev = pci_find_device(sab8253x_vendor_id, sab8253x_cpci_device_id, XX20lastpdev), 1146 pdev == NULL) 1147 { 1148 printk(KERN_ALERT "auraXX20n: could not find cpci card.\n"); 1149 kfree(bptr); 1150 return 0; 1151 } 1152 1153 DEBUGPRINT((KERN_ALERT "auraXX20n: found multiport CPCI serial card.\n")); 1154 1155 XX20lastpdev = pdev; 1156 DEBUGPRINT((KERN_ALERT "auraXX20n: found ATI PLX 9050, %p.\n", pdev)); 1157 bptr->b_dev = *pdev; 1158 1159 /* the Solaris and model linux drivers 1160 * comment that there are problems with 1161 * getting the length via PCI operations 1162 * seems to work for 2.4 1163 */ 1164 bptr->length0 = (unsigned int) pci_resource_len(pdev, 0); 1165 bptr->length1 = (unsigned int) pci_resource_len(pdev, 1); 1166 bptr->length2 = (unsigned int) pci_resource_len(pdev, 2); 1167 bptr->b_irq = pdev->irq; 1168 1169 1170 DEBUGPRINT((KERN_ALERT 1171 "auraXX20n: base address 0 is %p, len is %x.\n", 1172 (void*) pci_base_address(pdev, 0), bptr->length0)); 1173 DEBUGPRINT((KERN_ALERT 1174 "auraXX20n: base address 1 is %p, len is %x.\n", 1175 (void*) pci_base_address(pdev, 1), bptr->length1)); 1176 DEBUGPRINT((KERN_ALERT 1177 "auraXX20n: base address 2 is %p, len is %x.\n", 1178 (void*) pci_base_address(pdev, 2), 1179 bptr->length2)); 1180 1181 DEBUGPRINT((KERN_ALERT "auraXX20n: interrupt is %i.\n", pdev->irq)); 1182 bus = pdev->bus->number; 1183 devfn = pdev->devfn; 1184 DEBUGPRINT((KERN_ALERT "auraXX20n: bus is %x, slot is %x.\n", bus, PCI_SLOT(devfn))); 1185 pcibios_read_config_word(bus, devfn, PCI_COMMAND, &pci_command); 1186 if((pci_command & PCI_COMMAND_MASTER) != PCI_COMMAND_MASTER) 1187 { 1188 DEBUGPRINT((KERN_ALERT "auraXX20n: Aurora card is not a bus master.\n")); 1189 } 1190 1191 pcibios_read_config_byte(bus, devfn, PCI_LATENCY_TIMER, 1192 &pci_latency); 1193 if (pci_latency < 32) 1194 { 1195 DEBUGPRINT 1196 ((KERN_ALERT 1197 "auraXX20n: PCI latency timer (CFLT) is low at %i.\n", pci_latency)); 1198 /* may need to change the latency */ 1199 } 1200 else 1201 { 1202 DEBUGPRINT((KERN_ALERT 1203 "auraXX20n: PCI latency timer (CFLT) is %#x.\n", 1204 pci_latency)); 1205 } 1206 bptr->virtbaseaddress0 = ioremap_nocache(pci_base_address(pdev, 0), 1207 bptr->length0); 1208 if(bptr->virtbaseaddress0 == NULL) 1209 { 1210 printk(KERN_ALERT 1211 "auraXX20n: unable to remap physical address %p.\n", 1212 (void*) pci_base_address(pdev, 0)); 1213 1214 goto CPCIRESTART; 1215 } 1216 1217 bptr->b_bridge = (PLX9050*) bptr->virtbaseaddress0; /* MAKE SURE INTS ARE OFF */ 1218 writel(PLX_INT_OFF, &(bptr->b_bridge->intr)); 1219 1220 printk 1221 (KERN_ALERT 1222 "auraXX20n: remapped physical address %p to virtual address %p.\n", 1223 (void*) pci_base_address(pdev, 0), (void*) bptr->virtbaseaddress0); 1224 1225 dump_ati_adapter_registers((unsigned int*) bptr->virtbaseaddress0, bptr->length0); 1226 1227 if(*(unsigned int*)bptr->virtbaseaddress0 == -1) /* XP7 problem? */ 1228 { 1229 printk(KERN_ALERT 1230 "auraXX20n: unable to access PLX 9050 registers at %p.\n", 1231 (void*)bptr->virtbaseaddress0); 1232 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n", 1233 (void*)bptr->virtbaseaddress0); 1234 iounmap((void*)bptr->virtbaseaddress0); 1235 bptr->virtbaseaddress0 = 0; 1236 1237 goto CPCIRESTART; 1238 } 1239 1240 bptr->virtbaseaddress2 = ioremap_nocache(pci_base_address(pdev, 2), 1241 bptr->length2); 1242 if(bptr->virtbaseaddress2 == NULL) 1243 { 1244 printk(KERN_ALERT 1245 "auraXX20n: unable to remap physical address %p.\n", 1246 (void*) pci_base_address(pdev, 2)); 1247 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n", 1248 (void*)bptr->virtbaseaddress0); 1249 iounmap((void*)bptr->virtbaseaddress0); 1250 bptr->virtbaseaddress0 = 0; 1251 1252 goto CPCIRESTART; 1253 } 1254 1255 DEBUGPRINT 1256 ((KERN_ALERT 1257 "auraXX20n: remapped physical address %p to virtual address %p.\n", 1258 (void*) pci_base_address(pdev, 2), (void*) bptr->virtbaseaddress2)); 1259 1260 /* we get clockrate from serial eeprom */ 1261 if (!plx9050_eprom_read(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl, 1262 (unsigned short*) bptr->b_eprom, 1263 (unsigned char) 0, EPROM9050_SIZE)) 1264 { 1265 printk(KERN_ALERT "auraXX20n: Could not read serial eprom.\n"); 1266 iounmap((void*)bptr->virtbaseaddress0); 1267 bptr->virtbaseaddress0 = 0; 1268 iounmap((void*)bptr->virtbaseaddress2); 1269 bptr->virtbaseaddress2 = 0; 1270 1271 goto CPCIRESTART; 1272 } 1273 1274 printk(KERN_ALERT "auraXX20n: dumping serial eprom.\n"); 1275 dump_ati_adapter_registers((unsigned int*) bptr->b_eprom, 2 * EPROM9050_SIZE); 1276 1277 if(*(unsigned int*)bptr->b_eprom != PCIMEMVALIDCPCI) /* bridge problem? */ 1278 { 1279 printk(KERN_ALERT "auraXX20n: unable to access valid serial eprom data.\n"); 1280 iounmap((void*)bptr->virtbaseaddress0); 1281 bptr->virtbaseaddress0 = 0; 1282 iounmap((void*)bptr->virtbaseaddress2); 1283 bptr->virtbaseaddress2 = 0; 1284 1285 goto CPCIRESTART; 1286 } 1287 1288 if(((unsigned short*) bptr->b_eprom)[EPROMPREFETCHOFFSET] & PREFETCHBIT) 1289 { 1290 ++sab8253x_rebootflag; 1291 printk(KERN_ALERT "8253x: eeprom programmed for prefetchable memory resources; must reprogram!!\n"); 1292 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl, 1293 NM93_WENCMD, NM93_WENADDR, 0); 1294 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl, 1295 NM93_WRITECMD, 1296 9, 1297 (((unsigned short*) bptr->b_eprom)[EPROMPREFETCHOFFSET] & (~PREFETCHBIT))); 1298 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl, 1299 NM93_WDSCMD, NM93_WDSADDR, 0); 1300 } 1301 /* get SYNC and ONEPORT values */ 1302 1303 control = readl(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl); 1304 /* note we use the actual address 1305 * of the control register in 1306 * memory 1307 */ 1308 1309 if(control & AURORA_MULTI_SYNCBIT) 1310 { 1311 does_sync = 0; 1312 } 1313 else 1314 { 1315 does_sync = 1; 1316 } 1317 1318 if(control & AURORA_MULTI_1PORTBIT) 1319 { 1320 use_1port = 1; 1321 } 1322 else 1323 { 1324 use_1port = 0; 1325 } 1326 1327 1328 /* Figure out the board */ 1329 switch(bptr->length2) 1330 { 1331 case AURORA_4X20_SIZE: 1332 if(does_sync) 1333 { 1334 bptr->b_type = BD_4520CP; 1335 bptr->b_nchips = 2; 1336 bptr->b_nports = 4; 1337 bptr->b_flags = BD_SYNC; 1338 bptr->b_cimbase = NULL; 1339 bptr->board_number = BD4520CPcounter; /* keep track of boardnumber for naming devices */ 1340 ++BD4520CPcounter; 1341 printk(KERN_ALERT "auraXX20n: Found Saturn 4520CP.\n"); 1342 } 1343 else 1344 { 1345 bptr->b_type = BD_4020CP; 1346 bptr->b_nchips = 2; 1347 bptr->b_nports = 4; 1348 bptr->b_flags = 0x0; 1349 bptr->b_cimbase = NULL; 1350 bptr->board_number = BD4020CPcounter; 1351 ++BD4020CPcounter; 1352 printk(KERN_ALERT "auraXX20n: Found Apollo 4020CP.\n"); 1353 } 1354 break; 1355 case AURORA_8X20_SIZE: 1356 if(does_sync) 1357 { 1358 bptr->b_type = BD_8520CP; 1359 bptr->b_nchips = 1; 1360 bptr->b_nports = 8; 1361 bptr->b_flags = BD_SYNC; 1362 bptr->b_cimbase = NULL; 1363 bptr->board_number = BD8520CPcounter; 1364 ++BD8520CPcounter; 1365 printk(KERN_ALERT "auraXX20n: Found Saturn 8520CP.\n"); 1366 } 1367 else 1368 { 1369 bptr->b_type = BD_8020CP; 1370 bptr->b_nchips = 1; 1371 bptr->b_nports = 8; 1372 bptr->b_flags = 0x0; 1373 bptr->b_cimbase = NULL; 1374 bptr->board_number = BD8020CPcounter; 1375 ++BD8020CPcounter; 1376 printk(KERN_ALERT "auraXX20n: Found Apollo 8020CP.\n"); 1377 } 1378 break; 1379 case AURORA_2X20_SIZE: 1380 if(does_sync) 1381 { 1382 if(use_1port) 1383 { 1384 bptr->b_type = BD_1520CP; 1385 printk(KERN_ALERT "auraXX20n: Found Saturn 1520CP.\n"); 1386 bptr->b_nchips = 1; 1387 bptr->b_nports = 1; 1388 bptr->b_flags = BD_SYNC; 1389 bptr->b_cimbase = NULL; 1390 bptr->board_number = BD1520CPcounter; 1391 ++BD1520CPcounter; 1392 printk(KERN_ALERT "auraXX20n: Found Saturn 1520CP.\n"); 1393 } 1394 else 1395 { 1396 bptr->b_type = BD_2520CP; 1397 bptr->b_nchips = 1; 1398 bptr->b_nports = 2; 1399 bptr->b_flags = BD_SYNC; 1400 bptr->b_cimbase = NULL; 1401 bptr->board_number = BD2520CPcounter; 1402 ++BD2520CPcounter; 1403 printk(KERN_ALERT "auraXX20n: Found Saturn 2520CP.\n"); 1404 } 1405 } 1406 else 1407 { 1408 if(use_1port) 1409 { 1410 bptr->b_type = BD_1020CP; 1411 bptr->b_nchips = 1; 1412 bptr->b_nports = 1; 1413 bptr->b_flags = 0x0; 1414 bptr->b_cimbase = NULL; 1415 bptr->board_number = BD1020CPcounter; 1416 ++BD1020CPcounter; 1417 printk(KERN_ALERT "auraXX20n: Found Apollo 1020CP.\n"); 1418 } 1419 else 1420 { 1421 bptr->b_type = BD_2020CP; 1422 bptr->b_nchips = 1; 1423 bptr->b_nports = 2; 1424 bptr->b_flags = 0x0; 1425 bptr->b_cimbase = NULL; 1426 bptr->board_number = BD2020CPcounter; 1427 ++BD2020CPcounter; 1428 printk(KERN_ALERT "auraXX20n: Found Apollo 2020CP.\n"); 1429 } 1430 } 1431 break; 1432 default: 1433 printk(KERN_ALERT "Error: Board could not be identified\n"); 1434 iounmap((void*)bptr->virtbaseaddress0); 1435 bptr->virtbaseaddress0 = 0; 1436 iounmap((void*)bptr->virtbaseaddress2); 1437 bptr->virtbaseaddress2 = 0; 1438 1439 goto CPCIRESTART; 1440 } 1441 1442 /* Let's get the clockrate right -- ugh!*/ 1443 1444 bptr->b_clkspeed = bptr->b_eprom[AURORA_MULTI_EPROM_CLKLSW/2]; 1445 1446 if(bptr->b_clkspeed == -1) /* misprogrammed -- ugh. */ 1447 { 1448 switch(bptr->b_type) 1449 { 1450 case BD_8520CP: 1451 case BD_8020CP: 1452 bptr->b_clkspeed = AURORA_MULTI_CLKSPEED/4; 1453 break; 1454 default: 1455 bptr->b_clkspeed = AURORA_MULTI_CLKSPEED; 1456 break; 1457 1458 } 1459 printk(KERN_ALERT "auraXX20n: UNKNOWN CLOCKSPEED -- ASSUMING %ld.\n", bptr->b_clkspeed); 1460 1461 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl, 1462 NM93_WENCMD, NM93_WENADDR, 0); 1463 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl, 1464 NM93_WRITECMD, 1465 54, (unsigned short) bptr->b_clkspeed); 1466 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl, 1467 NM93_WRITECMD, 1468 55, (unsigned short) (bptr->b_clkspeed >> 16)); 1469 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl, 1470 NM93_WDSCMD, NM93_WDSADDR, 0); 1471 } 1472 1473 return bptr; 1474} 1475 1476static SAB_BOARD* find_ati_wanms_card(void) /* wan multichanner server == mcs [ multichannel server] */ 1477{ 1478 struct pci_dev *pdev; 1479 unsigned char bus; 1480 unsigned char devfn; 1481 unsigned char pci_latency; 1482 unsigned short pci_command; 1483 SAB_BOARD *bptr; 1484 int resetresult; 1485 1486 printk(KERN_ALERT "auraXX20n: finding ati mcs cards.\n"); 1487 1488 bptr = (SAB_BOARD*)kmalloc(sizeof(SAB_BOARD), GFP_KERNEL); 1489 if(bptr == NULL) 1490 { 1491 printk(KERN_ALERT "auraXX20n: could not allocate board memory!\n"); 1492 return 0; 1493 } 1494 memset(bptr, 0, sizeof(SAB_BOARD)); 1495 1496 if(!pcibios_present()) 1497 { 1498 printk(KERN_ALERT "auraXX20n: system does not support PCI bus.\n"); 1499 kfree(bptr); 1500 return 0; 1501 } 1502 DEBUGPRINT((KERN_ALERT "auraXX20n: System supports PCI bus.\n")); 1503 1504 MCSRESTART: 1505 if(pdev = pci_find_device(sab8253x_vendor_id, sab8253x_wmcs_device_id, XX20lastpdev), 1506 pdev == NULL) 1507 { 1508 printk(KERN_ALERT "auraXX20n: could not find mcs card.\n"); 1509 kfree(bptr); 1510 return 0; 1511 } 1512 1513 DEBUGPRINT((KERN_ALERT "auraXX20n: found mcs card.\n")); 1514 1515 XX20lastpdev = pdev; 1516 DEBUGPRINT((KERN_ALERT "auraXX20n: found ATI S5920, %p.\n", pdev)); 1517 bptr->b_dev = *pdev; 1518 1519 /* the Solaris and model linux drivers 1520 * comment that there are problems with 1521 * getting the length via PCI operations 1522 * seems to work for 2.4 1523 */ 1524 bptr->length0 = (unsigned int) pci_resource_len(pdev, 0); /* AMCC 5920 operation registers 1525 includes access to serial eprom */ 1526 bptr->length1 = (unsigned int) pci_resource_len(pdev, 1); /* commands to remote cards */ 1527 bptr->length2 = (unsigned int) pci_resource_len(pdev, 2); /* command to host card */ 1528 bptr->length3 = (unsigned int) pci_resource_len(pdev, 3); /* RFIFO cache */ 1529 bptr->b_irq = pdev->irq; 1530 1531 DEBUGPRINT((KERN_ALERT 1532 "auraXX20n: base address 0 is %p, len is %x.\n", 1533 (void*) pci_base_address(pdev, 0), bptr->length0)); 1534 DEBUGPRINT((KERN_ALERT 1535 "auraXX20n: base address 1 is %p, len is %x.\n", 1536 (void*) pci_base_address(pdev, 1), bptr->length1)); 1537 DEBUGPRINT((KERN_ALERT 1538 "auraXX20n: base address 2 is %p, len is %x.\n", 1539 (void*) pci_base_address(pdev, 2), 1540 bptr->length2)); 1541 DEBUGPRINT((KERN_ALERT 1542 "auraXX20n: base address 3 is %p, len is %x.\n", 1543 (void*) pci_base_address(pdev, 3), 1544 bptr->length3)); 1545 1546 DEBUGPRINT((KERN_ALERT "auraXX20n: interrupt is %i.\n", pdev->irq)); 1547 bus = pdev->bus->number; 1548 devfn = pdev->devfn; 1549 DEBUGPRINT((KERN_ALERT "auraXX20n: bus is %x, slot is %x.\n", bus, PCI_SLOT(devfn))); 1550 pcibios_read_config_word(bus, devfn, PCI_COMMAND, &pci_command); 1551 1552 1553 if((pci_command & PCI_COMMAND_MASTER) != PCI_COMMAND_MASTER) 1554 { 1555 DEBUGPRINT((KERN_ALERT "auraXX20n: Aurora card is not a bus master.\n")); 1556 } 1557 1558 pcibios_read_config_byte(bus, devfn, PCI_LATENCY_TIMER, 1559 &pci_latency); 1560 if (pci_latency < 32) 1561 { 1562 DEBUGPRINT 1563 ((KERN_ALERT 1564 "auraXX20n: PCI latency timer (CFLT) is low at %i.\n", pci_latency)); 1565 /* may need to change the latency */ 1566 } 1567 else 1568 { 1569 DEBUGPRINT((KERN_ALERT 1570 "auraXX20n: PCI latency timer (CFLT) is %#x.\n", 1571 pci_latency)); 1572 } 1573 1574 bptr->virtbaseaddress0 = ioremap_nocache(pci_base_address(pdev, 0), 1575 bptr->length0); 1576 if(bptr->virtbaseaddress0 == NULL) 1577 { 1578 printk(KERN_ALERT 1579 "auraXX20n: unable to remap physical address %p.\n", 1580 (void*) pci_base_address(pdev, 0)); 1581 goto MCSRESTART; 1582 } 1583 1584 bptr->b_bridge = (void*) bptr->virtbaseaddress0; /* b_bridge is not supposed 1585 to be used by the AMCC based 1586 products -- it is set just 1587 in case */ 1588 1589 printk(KERN_ALERT 1590 "auraXX20n: remapped physical address %p to virtual address %p.\n", 1591 (void*) pci_base_address(pdev, 0), (void*) bptr->virtbaseaddress0); 1592 1593 /* unfortunate name -- works for any bridge */ 1594 dump_ati_adapter_registers((unsigned int*) bptr->virtbaseaddress0, bptr->length0); 1595 1596 if(*(unsigned int*)bptr->virtbaseaddress0 == -1) /* XP7 problem? */ 1597 { 1598 printk(KERN_ALERT 1599 "auraXX20n: unable to access AMCC registers at %p.\n", 1600 (void*)bptr->virtbaseaddress0); 1601 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n", 1602 (void*)bptr->virtbaseaddress0); 1603 iounmap((void*)bptr->virtbaseaddress0); 1604 bptr->virtbaseaddress0 = 0; 1605 goto MCSRESTART; /* try the next one if any */ 1606 } 1607 1608 writel(AMCC_INT_OFF, (unsigned int*)(bptr->AMCC_REG + AMCC_INTCSR)); 1609 1610 bptr->virtbaseaddress1 = ioremap_nocache(pci_base_address(pdev, 1), 1611 bptr->length1); 1612 if(bptr->virtbaseaddress1 == NULL) 1613 { 1614 printk(KERN_ALERT 1615 "auraXX20n: unable to remap physical address %p.\n", 1616 (void*) pci_base_address(pdev, 1)); 1617 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n", 1618 (void*)bptr->virtbaseaddress0); 1619 iounmap((void*)bptr->virtbaseaddress0); 1620 bptr->virtbaseaddress0 = 0; 1621 goto MCSRESTART; 1622 } 1623 1624 DEBUGPRINT 1625 ((KERN_ALERT 1626 "auraXX20n: remapped physical address %p to virtual address %p.\n", 1627 (void*) pci_base_address(pdev, 1), (void*) bptr->virtbaseaddress1)); 1628 1629 /* next address space */ 1630 bptr->virtbaseaddress2 = ioremap_nocache(pci_base_address(pdev, 2), 1631 bptr->length2); 1632 if(bptr->virtbaseaddress2 == NULL) 1633 { 1634 printk(KERN_ALERT 1635 "auraXX20n: unable to remap physical address %p.\n", 1636 (void*) pci_base_address(pdev, 2)); 1637 1638 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n", 1639 (void*)bptr->virtbaseaddress0); 1640 iounmap((void*)bptr->virtbaseaddress0); 1641 bptr->virtbaseaddress0 = 0; 1642 1643 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n", 1644 (void*)bptr->virtbaseaddress1); 1645 iounmap((void*)bptr->virtbaseaddress1); 1646 bptr->virtbaseaddress1 = 0; 1647 goto MCSRESTART; 1648 } 1649 1650 DEBUGPRINT 1651 ((KERN_ALERT 1652 "auraXX20n: remapped physical address %p to virtual address %p.\n", 1653 (void*) pci_base_address(pdev, 2), (void*) bptr->virtbaseaddress2)); 1654 1655 bptr->virtbaseaddress3 = ioremap_nocache(pci_base_address(pdev, 3), 1656 bptr->length3); 1657 if(bptr->virtbaseaddress3 == NULL) 1658 { 1659 printk(KERN_ALERT 1660 "auraXX20n: unable to remap physical address %p.\n", 1661 (void*) pci_base_address(pdev, 3)); 1662 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n", 1663 (void*)bptr->virtbaseaddress0); 1664 iounmap((void*)bptr->virtbaseaddress0); 1665 bptr->virtbaseaddress0 = 0; 1666 1667 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n", 1668 (void*)bptr->virtbaseaddress1); 1669 iounmap((void*)bptr->virtbaseaddress1); 1670 bptr->virtbaseaddress1 = 0; 1671 1672 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n", 1673 (void*)bptr->virtbaseaddress2); 1674 iounmap((void*)bptr->virtbaseaddress2); 1675 bptr->virtbaseaddress2 = 0; 1676 1677 goto MCSRESTART; 1678 } 1679 1680 DEBUGPRINT 1681 ((KERN_ALERT 1682 "auraXX20n: remapped physical address %p to virtual address %p.\n", 1683 (void*) pci_base_address(pdev, 3), (void*) bptr->virtbaseaddress3)); 1684 1685 bptr->b_type = BD_WANMCS; 1686 1687 resetresult = wanmcs_reset(bptr); 1688 writel(AMCC_INT_OFF, (unsigned int*)(bptr->AMCC_REG + AMCC_INTCSR)); 1689 1690 if(resetresult == FALSE) 1691 { 1692 printk(KERN_ALERT "auraXX20n: unable to reset wan mcs %p.\n", bptr); 1693 1694 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n", 1695 (void*)bptr->virtbaseaddress0); 1696 iounmap((void*)bptr->virtbaseaddress0); 1697 bptr->virtbaseaddress0 = 0; 1698 1699 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n", 1700 (void*)bptr->virtbaseaddress1); 1701 iounmap((void*)bptr->virtbaseaddress1); 1702 bptr->virtbaseaddress1 = 0; 1703 1704 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n", 1705 (void*)bptr->virtbaseaddress2); 1706 iounmap((void*)bptr->virtbaseaddress2); 1707 bptr->virtbaseaddress2 = 0; 1708 1709 1710 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n", 1711 (void*)bptr->virtbaseaddress3); 1712 iounmap((void*)bptr->virtbaseaddress3); 1713 bptr->virtbaseaddress3 = 0; 1714 1715 goto MCSRESTART; 1716 } 1717 1718 /* we get clockrate from serial eeprom */ 1719 if (amcc_read_nvram((unsigned char*) bptr->b_eprom, 1720 AMCC_NVRAM_SIZE, bptr->AMCC_REG) == FALSE) 1721 { 1722 printk(KERN_ALERT "auraXX20n: Could not read serial eprom.\n"); 1723 iounmap((void*)bptr->virtbaseaddress0); 1724 bptr->virtbaseaddress0 = 0; 1725 iounmap((void*)bptr->virtbaseaddress1); 1726 bptr->virtbaseaddress1 = 0; 1727 iounmap((void*)bptr->virtbaseaddress2); 1728 bptr->virtbaseaddress2 = 0; 1729 iounmap((void*)bptr->virtbaseaddress3); 1730 bptr->virtbaseaddress3 = 0; 1731 goto MCSRESTART; 1732 } 1733 printk(KERN_ALERT "auraXX20n: dumping serial eprom.\n"); 1734 dump_ati_adapter_registers((unsigned int*) bptr->b_eprom, 2 * AMCC_NVRAM_SIZE); 1735 if(bptr->b_eprom[AMCC_NVR_VENDEVID] != PCIMEMVALIDWMCS) 1736 { 1737 printk(KERN_ALERT "auraXX20: bad serial eprom, board %p.\n", bptr); 1738 iounmap((void*)bptr->virtbaseaddress0); 1739 bptr->virtbaseaddress0 = 0; 1740 iounmap((void*)bptr->virtbaseaddress1); 1741 bptr->virtbaseaddress1 = 0; 1742 iounmap((void*)bptr->virtbaseaddress2); 1743 bptr->virtbaseaddress2 = 0; 1744 iounmap((void*)bptr->virtbaseaddress3); 1745 bptr->virtbaseaddress3 = 0; 1746 goto MCSRESTART; 1747 } 1748 return bptr; 1749} 1750 1751/* initialize the auraXX20 */ 1752static SAB_BOARD* find_ati_multiport_card(void) 1753{ 1754 struct pci_dev *pdev; 1755 unsigned char bus; 1756 unsigned char devfn; 1757 unsigned char pci_latency; 1758 unsigned short pci_command; 1759 SAB_BOARD *bptr; 1760 unsigned control; 1761 unsigned does_sync; 1762 unsigned use_1port; 1763 1764 printk(KERN_ALERT "auraXX20n: finding ati cards.\n"); 1765 1766 bptr = (SAB_BOARD*)kmalloc(sizeof(SAB_BOARD), GFP_KERNEL); 1767 if(bptr == NULL) 1768 { 1769 printk(KERN_ALERT "auraXX20n: could not allocate board memory!\n"); 1770 return 0; 1771 } 1772 memset(bptr, 0, sizeof(SAB_BOARD)); 1773 1774 if(!pcibios_present()) 1775 { 1776 printk(KERN_ALERT "auraXX20n: system does not support PCI bus.\n"); 1777 kfree(bptr); 1778 return 0; 1779 } 1780 DEBUGPRINT((KERN_ALERT "auraXX20n: System supports PCI bus.\n")); 1781 1782 MULTIPORTRESTART: 1783 if(pdev = pci_find_device(sab8253x_vendor_id, sab8253x_mpac_device_id, XX20lastpdev), 1784 pdev == NULL) 1785 { 1786 printk(KERN_ALERT "auraXX20n: could not find multiport card.\n"); 1787 kfree(bptr); 1788 return 0; 1789 } 1790 1791 DEBUGPRINT((KERN_ALERT "auraXX20n: found multiport PCI serial card.\n")); 1792 1793 XX20lastpdev = pdev; 1794 DEBUGPRINT((KERN_ALERT "auraXX20n: found ATI PLX 9050, %p.\n", pdev)); 1795 bptr->b_dev = *pdev; 1796 1797 /* the Solaris and model linux drivers 1798 * comment that there are problems with 1799 * getting the length via PCI operations 1800 * seems to work for 2.4 1801 */ 1802 bptr->length0 = (unsigned int) pci_resource_len(pdev, 0); 1803 bptr->length1 = (unsigned int) pci_resource_len(pdev, 1); 1804 bptr->length2 = (unsigned int) pci_resource_len(pdev, 2); 1805 bptr->b_irq = pdev->irq; 1806 1807 1808 DEBUGPRINT((KERN_ALERT 1809 "auraXX20n: base address 0 is %p, len is %x.\n", 1810 (void*) pci_base_address(pdev, 0), bptr->length0)); 1811 DEBUGPRINT((KERN_ALERT 1812 "auraXX20n: base address 1 is %p, len is %x.\n", 1813 (void*) pci_base_address(pdev, 1), bptr->length1)); 1814 DEBUGPRINT((KERN_ALERT 1815 "auraXX20n: base address 2 is %p, len is %x.\n", 1816 (void*) pci_base_address(pdev, 2), 1817 bptr->length2)); 1818 1819 DEBUGPRINT((KERN_ALERT "auraXX20n: interrupt is %i.\n", pdev->irq)); 1820 bus = pdev->bus->number; 1821 devfn = pdev->devfn; 1822 DEBUGPRINT((KERN_ALERT "auraXX20n: bus is %x, slot is %x.\n", bus, PCI_SLOT(devfn))); 1823 pcibios_read_config_word(bus, devfn, PCI_COMMAND, &pci_command); 1824 if((pci_command & PCI_COMMAND_MASTER) != PCI_COMMAND_MASTER) 1825 { 1826 DEBUGPRINT((KERN_ALERT "auraXX20n: Aurora card is not a bus master.\n")); 1827 } 1828 1829 pcibios_read_config_byte(bus, devfn, PCI_LATENCY_TIMER, 1830 &pci_latency); 1831 if (pci_latency < 32) 1832 { 1833 DEBUGPRINT 1834 ((KERN_ALERT 1835 "auraXX20n: PCI latency timer (CFLT) is low at %i.\n", pci_latency)); 1836 /* may need to change the latency */ 1837 } 1838 else 1839 { 1840 DEBUGPRINT((KERN_ALERT 1841 "auraXX20n: PCI latency timer (CFLT) is %#x.\n", 1842 pci_latency)); 1843 } 1844 bptr->virtbaseaddress0 = ioremap_nocache(pci_base_address(pdev, 0), 1845 bptr->length0); 1846 if(bptr->virtbaseaddress0 == NULL) 1847 { 1848 printk(KERN_ALERT 1849 "auraXX20n: unable to remap physical address %p.\n", 1850 (void*) pci_base_address(pdev, 0)); 1851 1852 goto MULTIPORTRESTART; 1853 } 1854 1855 bptr->b_bridge = (PLX9050*) bptr->virtbaseaddress0; /* MAKE SURE INTS ARE OFF */ 1856 writel(PLX_INT_OFF, &(bptr->b_bridge->intr)); 1857 1858 printk(KERN_ALERT 1859 "auraXX20n: remapped physical address %p to virtual address %p.\n", 1860 (void*) pci_base_address(pdev, 0), (void*) bptr->virtbaseaddress0); 1861 1862 dump_ati_adapter_registers((unsigned int*) bptr->virtbaseaddress0, bptr->length0); 1863 1864 if(*(unsigned int*)bptr->virtbaseaddress0 == -1) /* XP7 problem? */ 1865 { 1866 printk(KERN_ALERT 1867 "auraXX20n: unable to access PLX 9050 registers at %p.\n", 1868 (void*)bptr->virtbaseaddress0); 1869 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n", 1870 (void*)bptr->virtbaseaddress0); 1871 iounmap((void*)bptr->virtbaseaddress0); 1872 bptr->virtbaseaddress0 = 0; 1873 1874 goto MULTIPORTRESTART; 1875 } 1876 1877 bptr->virtbaseaddress2 = ioremap_nocache(pci_base_address(pdev, 2), 1878 bptr->length2); 1879 if(bptr->virtbaseaddress2 == NULL) 1880 { 1881 printk(KERN_ALERT 1882 "auraXX20n: unable to remap physical address %p.\n", 1883 (void*) pci_base_address(pdev, 2)); 1884 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n", 1885 (void*)bptr->virtbaseaddress0); 1886 iounmap((void*)bptr->virtbaseaddress0); 1887 bptr->virtbaseaddress0 = 0; 1888 1889 goto MULTIPORTRESTART; 1890 } 1891 1892 DEBUGPRINT((KERN_ALERT 1893 "auraXX20n: remapped physical address %p to virtual address %p.\n", 1894 (void*) pci_base_address(pdev, 2), (void*) bptr->virtbaseaddress2)); 1895 1896 if (!plx9050_eprom_read(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl, 1897 (unsigned short*) bptr->b_eprom, 1898 (unsigned char) 0, EPROM9050_SIZE)) 1899 { 1900 printk(KERN_ALERT "auraXX20n: Could not read serial eprom.\n"); 1901 iounmap((void*)bptr->virtbaseaddress0); 1902 bptr->virtbaseaddress0 = 0; 1903 iounmap((void*)bptr->virtbaseaddress2); 1904 bptr->virtbaseaddress2 = 0; 1905 1906 goto MULTIPORTRESTART; 1907 } 1908 1909 printk(KERN_ALERT "auraXX20n: dumping serial eprom.\n"); 1910 dump_ati_adapter_registers((unsigned int*) bptr->b_eprom, 2 * EPROM9050_SIZE); 1911 1912 if(*(unsigned int*)bptr->b_eprom != PCIMEMVALIDMULTI) /* bridge problem? */ 1913 { 1914 printk(KERN_ALERT "auraXX20n: unable to access valid serial eprom data.\n"); 1915 iounmap((void*)bptr->virtbaseaddress0); 1916 bptr->virtbaseaddress0 = 0; 1917 iounmap((void*)bptr->virtbaseaddress2); 1918 bptr->virtbaseaddress2 = 0; 1919 1920 goto MULTIPORTRESTART; 1921 } 1922 1923 if(((unsigned short*) bptr->b_eprom)[EPROMPREFETCHOFFSET] & PREFETCHBIT) 1924 { 1925 ++sab8253x_rebootflag; 1926 printk(KERN_ALERT "8253x: eeprom programmed for prefetchable memory resources; must reprogram!!\n"); 1927 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl, 1928 NM93_WENCMD, NM93_WENADDR, 0); 1929 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl, 1930 NM93_WRITECMD, 1931 9, 1932 (((unsigned short*) bptr->b_eprom)[EPROMPREFETCHOFFSET] & (~PREFETCHBIT))); 1933 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl, 1934 NM93_WDSCMD, NM93_WDSADDR, 0); 1935 } 1936 1937 /* get SYNC and ONEPORT values */ 1938 1939 control = readl(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl); 1940 /* note we use the actual address 1941 * of the control register in 1942 * memory 1943 */ 1944 1945 if(control & AURORA_MULTI_SYNCBIT) 1946 { 1947 does_sync = 0; 1948 } 1949 else 1950 { 1951 does_sync = 1; 1952 } 1953 1954 if(control & AURORA_MULTI_1PORTBIT) 1955 { 1956 use_1port = 1; 1957 } 1958 else 1959 { 1960 use_1port = 0; 1961 } 1962 1963 1964 /* Figure out the board */ 1965 switch(bptr->length2) 1966 { 1967 case AURORA_4X20_SIZE: 1968 if(does_sync) 1969 { 1970 bptr->b_type = BD_4520P; 1971 bptr->b_nchips = 2; 1972 bptr->b_nports = 4; 1973 bptr->b_flags = BD_SYNC; 1974 bptr->b_cimbase = NULL; 1975 bptr->board_number = BD4520Pcounter; /* keep track of boardnumber for naming devices */ 1976 ++BD4520Pcounter; 1977 printk(KERN_ALERT "auraXX20n: Found Saturn 4520P.\n"); 1978 } 1979 else 1980 { 1981 bptr->b_type = BD_4020P; 1982 bptr->b_nchips = 2; 1983 bptr->b_nports = 4; 1984 bptr->b_flags = 0x0; 1985 bptr->b_cimbase = NULL; 1986 bptr->board_number = BD4020Pcounter; 1987 ++BD4020Pcounter; 1988 printk(KERN_ALERT "auraXX20n: Found Apollo 4020P.\n"); 1989 } 1990 break; 1991 case AURORA_8X20_SIZE: 1992 if(does_sync) 1993 { 1994 bptr->b_type = BD_8520P; 1995 bptr->b_nchips = 1; 1996 bptr->b_nports = 8; 1997 bptr->b_flags = BD_SYNC; 1998 bptr->b_cimbase = NULL; 1999 bptr->board_number = BD8520Pcounter; 2000 ++BD8520Pcounter; 2001 printk(KERN_ALERT "auraXX20n: Found Saturn 8520P.\n"); 2002 } 2003 else 2004 { 2005 bptr->b_type = BD_8020P; 2006 bptr->b_nchips = 1; 2007 bptr->b_nports = 8; 2008 bptr->b_flags = 0x0; 2009 bptr->b_cimbase = NULL; 2010 bptr->board_number = BD8020Pcounter; 2011 ++BD8020Pcounter; 2012 printk(KERN_ALERT "auraXX20n: Found Apollo 8020P.\n"); 2013 } 2014 break; 2015 case AURORA_2X20_SIZE: 2016 if(does_sync) 2017 { 2018 if(use_1port) 2019 { 2020 bptr->b_type = BD_1520P; 2021 printk(KERN_ALERT "auraXX20n: Found Saturn 1520P.\n"); 2022 bptr->b_nchips = 1; 2023 bptr->b_nports = 1; 2024 bptr->b_flags = BD_SYNC; 2025 bptr->b_cimbase = NULL; 2026 bptr->board_number = BD1520Pcounter; 2027 ++BD1520Pcounter; 2028 printk(KERN_ALERT "auraXX20n: Found Saturn 1520P.\n"); 2029 } 2030 else 2031 { 2032 bptr->b_type = BD_2520P; 2033 bptr->b_nchips = 1; 2034 bptr->b_nports = 2; 2035 bptr->b_flags = BD_SYNC; 2036 bptr->b_cimbase = NULL; 2037 bptr->board_number = BD2520Pcounter; 2038 ++BD2520Pcounter; 2039 printk(KERN_ALERT "auraXX20n: Found Saturn 2520P.\n"); 2040 } 2041 } 2042 else 2043 { 2044 if(use_1port) 2045 { 2046 bptr->b_type = BD_1020P; 2047 bptr->b_nchips = 1; 2048 bptr->b_nports = 1; 2049 bptr->b_flags = 0x0; 2050 bptr->b_cimbase = NULL; 2051 bptr->board_number = BD1020Pcounter; 2052 ++BD1020Pcounter; 2053 printk(KERN_ALERT "auraXX20n: Found Apollo 1020P.\n"); 2054 } 2055 else 2056 { 2057 bptr->b_type = BD_2020P; 2058 bptr->b_nchips = 1; 2059 bptr->b_nports = 2; 2060 bptr->b_flags = 0x0; 2061 bptr->b_cimbase = NULL; 2062 bptr->board_number = BD2020Pcounter; 2063 ++BD2020Pcounter; 2064 printk(KERN_ALERT "auraXX20n: Found Apollo 2020P.\n"); 2065 } 2066 } 2067 break; 2068 default: 2069 printk(KERN_ALERT "Error: Board could not be identified\n"); 2070 iounmap((void*)bptr->virtbaseaddress0); 2071 bptr->virtbaseaddress0 = 0; 2072 iounmap((void*)bptr->virtbaseaddress2); 2073 bptr->virtbaseaddress2 = 0; 2074 2075 goto MULTIPORTRESTART; 2076 } 2077 /* Let's get the clockrate right -- ugh!*/ 2078 2079 bptr->b_clkspeed = bptr->b_eprom[AURORA_MULTI_EPROM_CLKLSW/2]; 2080 2081 if(bptr->b_clkspeed == -1) /* misprogrammed -- ugh. */ 2082 { 2083 switch(bptr->b_type) 2084 { 2085 case BD_8520P: 2086 case BD_8020P: 2087 bptr->b_clkspeed = AURORA_MULTI_CLKSPEED/4; 2088 break; 2089 default: 2090 bptr->b_clkspeed = AURORA_MULTI_CLKSPEED; 2091 break; 2092 2093 } 2094 printk(KERN_ALERT "auraXX20n: UNKNOWN CLOCKSPEED -- ASSUMING %ld.\n", bptr->b_clkspeed); 2095 2096 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl, 2097 NM93_WENCMD, NM93_WENADDR, 0); 2098 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl, 2099 NM93_WRITECMD, 2100 54, (unsigned short) bptr->b_clkspeed); 2101 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl, 2102 NM93_WRITECMD, 2103 55, (bptr->b_clkspeed >> 16)); 2104 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl, 2105 NM93_WDSCMD, NM93_WDSADDR, 0); 2106 } 2107 2108 return bptr; 2109} 2110 2111#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0) 2112#ifdef MODULE 2113int init_module(void) /* all OS */ 2114#else 2115int auraXX20_probe(struct net_device *devp) /* passed default device structure */ 2116#endif 2117#else 2118static int __init auraXX20_probe(void) /* legacy device initialization 2.4.* */ 2119#endif 2120{ 2121 SAB_BOARD *boardptr; 2122 SAB_PORT *portptr; 2123 struct net_device *dev; 2124 unsigned int result; 2125 unsigned int namelength; 2126 unsigned int portno; 2127 int intr_val; 2128 2129 int mp_probe_count = 0; /* multiport count */ 2130 int cp_probe_count = 0; /* compact pci count */ 2131 int wm_probe_count = 0; /* wan multiserver count */ 2132 2133 printk(KERN_ALERT "aurora interea miseris mortalibus almam extulerat lucem\n"); 2134 printk(KERN_ALERT " referens opera atque labores\n"); 2135 2136 memset(AuraBoardESCC8IrqRoot, 0, sizeof(AuraBoardESCC8IrqRoot)); 2137 memset(AuraBoardESCC2IrqRoot, 0, sizeof(AuraBoardESCC2IrqRoot)); 2138 memset(AuraBoardMCSIrqRoot, 0, sizeof(AuraBoardMCSIrqRoot)); 2139 2140#if !defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0)) 2141 if(do_probe == 0) 2142 return -1; /* only allow to be called one 2.2.* */ 2143 do_probe = 0; 2144#endif 2145 2146 fn_init_crc_table(); /* used in faking ethernet packets for */ 2147 /* the network driver -- crcs are currently */ 2148 /* not being checked by this software */ 2149 /* but is good to have them in case a frame */ 2150 /* passes through a WAN LAN bridge */ 2151 2152 sab8253x_setup_ttydriver(); /* add synchronous tty and synchronous network 2153 driver initialization */ 2154 2155 AuraBoardRoot = NULL; /* basic lists */ 2156 AuraChipRoot = NULL; 2157 AuraPortRoot = NULL; 2158 NumSab8253xPorts = 0; 2159 2160 AuraXX20DriverParams.debug = auraXX20n_debug; 2161 AuraXX20DriverParams.listsize = sab8253xn_listsize; 2162 2163 if(auraXX20n_name != 0) 2164 { 2165#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0) 2166 auraXX20n_prototype.name = auraXX20n_name; 2167#else 2168 strcpy(auraXX20n_prototype.name, auraXX20n_name); 2169#endif 2170 } 2171 2172 /* find all multiport cards */ 2173 XX20lastpdev = NULL; 2174 while(1) 2175 { 2176 boardptr = find_ati_multiport_card(); 2177 if(boardptr == NULL) 2178 { 2179 printk(KERN_ALERT 2180 "auraXX20n: found %d AURAXX20 multiport device%s.\n", 2181 mp_probe_count, ((mp_probe_count == 1) ? "" : "s")); 2182 break; 2183 } 2184 boardptr->nextboard = AuraBoardRoot; 2185 AuraBoardRoot = boardptr; 2186 printk(KERN_ALERT "auraXX20n: found AURAXX20 multiport device #%d.\n", 2187 mp_probe_count); 2188 ++mp_probe_count; 2189 } 2190 2191 /* find all cpci cards */ 2192 XX20lastpdev = NULL; 2193 while(1) 2194 { 2195 boardptr = find_ati_cpci_card(); 2196 if(boardptr == NULL) 2197 { 2198 printk(KERN_ALERT 2199 "auraXX20n: found %d AURAXX20 CPCI device%s.\n", 2200 cp_probe_count, ((cp_probe_count == 1) ? "" : "s")); 2201 break; 2202 } 2203 boardptr->nextboard = AuraBoardRoot; 2204 AuraBoardRoot = boardptr; 2205 printk(KERN_ALERT "auraXX20n: found AURAXX20 CPCI device #%d.\n", 2206 cp_probe_count); 2207 ++cp_probe_count; 2208 } 2209 /* find all WAN MS cards */ 2210 XX20lastpdev = NULL; 2211 while(1) 2212 { 2213 boardptr = find_ati_wanms_card(); 2214 if(boardptr == NULL) 2215 { 2216 printk(KERN_ALERT 2217 "auraXX20n: found %d AURAXX20 WANMS device%s.\n", 2218 wm_probe_count, ((wm_probe_count == 1) ? "" : "s")); 2219 break; 2220 } 2221 boardptr->nextboard = AuraBoardRoot; 2222 AuraBoardRoot = boardptr; 2223 printk(KERN_ALERT "auraXX20n: found AURAXX20 WANMS device #%d.\n", 2224 wm_probe_count); 2225 ++wm_probe_count; 2226 } 2227 2228 /* Now do the chips! */ 2229 2230 for(boardptr = AuraBoardRoot; boardptr != NULL; boardptr = boardptr->nextboard) 2231 { 2232 SetupAllChips(boardptr); /* sets up the ports on the chips */ 2233 } 2234 2235 /* set up global driver structures 2236 * for async tty, call out device 2237 * for sync tty and for network device 2238 */ 2239 2240 /* NOW TURN ON THE PLX INTS */ 2241 /* note all port ints (only receive right now) 2242 * are off */ 2243 2244 /* interrupts cannot be turned on by port 2245 this seems to be the only sensible place 2246 to do it*/ 2247 2248 /* only at this point is the number of 2249 * ttys to be created known. */ 2250 2251 if(finish_sab8253x_setup_ttydriver() == -1) /* only as many termios are allocated */ 2252 /* as needed */ 2253 { 2254 return 0; 2255 } 2256 for(portno = 0, portptr = AuraPortRoot; portptr != NULL; ++portno, portptr = portptr->next) 2257 { 2258 portptr->line = portno; /* set up the line number == minor dev associated with port */ 2259 portptr->sigmode = sab8253x_default_sp502_mode; 2260 /* if we have SP502s let getty work with RS232 by default */ 2261 /* unless overridden in module setup. */ 2262 } 2263 /* Now lets set up the network devices */ 2264 for(portno = 0, portptr = AuraPortRoot; portptr != NULL; ++portno, portptr = portptr->next) 2265 { 2266 2267 dev = kmalloc(sizeof(struct net_device), GFP_KERNEL); 2268 if(!dev) 2269 { 2270 break; 2271 } 2272 memset(dev, 0, sizeof(struct net_device)); 2273 *dev = auraXX20n_prototype; 2274#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0) 2275 dev->name = kmalloc(IFNAMSIZ+1, GFP_KERNEL); 2276 if(!dev->name) 2277 { 2278 kfree(dev); 2279 break; 2280 } 2281#endif 2282 namelength = MIN(strlen(auraXX20n_prototype.name), IFNAMSIZ); 2283 strcpy(dev->name, auraXX20n_prototype.name); 2284 sprintf(&dev->name[namelength-1], "%3.3d", portno); 2285 2286 current_sab_port = portptr; 2287 result = register_netdev(dev); 2288 if(result) 2289 { /* if we run into some internal kernel limit */ 2290 break; 2291 } 2292 printk(KERN_ALERT "sab8253xn: found sab8253x network device #%d.\n", 2293 portno); 2294 } 2295 printk(KERN_ALERT 2296 "sab8253xn: found %d sab8253x network device%s.\n", 2297 portno, ((portno == 1) ? "" : "s")); 2298 2299 /* Now lets set up the character device */ 2300 2301 if(sab8253xc_name) 2302 { 2303 result = register_chrdev(sab8253xc_major, sab8253xc_name, &sab8253xc_fops); 2304 if(result < 0) 2305 { 2306 sab8253xc_major = result; 2307 printk(KERN_ALERT "Could not install sab8253xc device.\n"); 2308 } 2309 else if(result > 0) 2310 { 2311 sab8253xc_major = result; 2312 } 2313 } 2314 2315 for(boardptr = AuraBoardRoot; boardptr != NULL; boardptr = boardptr->nextboard) 2316 { /* let's set up port interrupt lists */ 2317 intr_val = boardptr->b_irq; 2318 if((intr_val < 0) || (intr_val >= NUMINTS)) 2319 { 2320 printk(KERN_ALERT "sab8253xn: bad interrupt %i board %p.\n", intr_val, boardptr); 2321 continue; 2322 } 2323 switch(boardptr->b_type) 2324 { 2325 case BD_WANMCS: 2326 boardptr->next_on_interrupt = AuraBoardMCSIrqRoot[intr_val]; 2327 AuraBoardMCSIrqRoot[intr_val] = boardptr; 2328 break; 2329 case BD_8520P: 2330 case BD_8520CP: 2331 boardptr->next_on_interrupt = AuraBoardESCC8IrqRoot[intr_val]; 2332 AuraBoardESCC8IrqRoot[intr_val] = boardptr; 2333 break; 2334 default: 2335 boardptr->next_on_interrupt = AuraBoardESCC2IrqRoot[intr_val]; 2336 AuraBoardESCC2IrqRoot[intr_val] = boardptr; 2337 break; 2338 } 2339 } 2340 2341 for(intr_val = 0; intr_val < NUMINTS; ++intr_val) /* trying to install as few int handlers as possible */ 2342 { /* one for each group of boards on a given irq */ 2343 if((AuraBoardESCC2IrqRoot[intr_val] != NULL) || (AuraBoardESCC8IrqRoot[intr_val] != NULL) || 2344 (AuraBoardMCSIrqRoot[intr_val] != NULL)) 2345 { 2346 if (request_irq(intr_val, sab8253x_interrupt, SA_SHIRQ, 2347 "sab8253x", &AuraBoardESCC2IrqRoot[intr_val]) == 0) 2348 /* interrupts on perboard basis 2349 * cycle through chips and then 2350 * ports */ 2351 /* NOTE PLX INTS ARE OFF -- so turn them on */ 2352 { 2353 for(boardptr = AuraBoardESCC2IrqRoot[intr_val]; boardptr != NULL; 2354 boardptr = boardptr->next_on_interrupt) 2355 { 2356 writel(PLX_INT_ON, &(boardptr->b_bridge->intr)); 2357 } 2358 for(boardptr = AuraBoardESCC8IrqRoot[intr_val]; boardptr != NULL; 2359 boardptr = boardptr->next_on_interrupt) 2360 { 2361 writel(PLX_INT_ON, &(boardptr->b_bridge->intr)); 2362 } 2363 for(boardptr = AuraBoardMCSIrqRoot[intr_val]; boardptr != NULL; 2364 boardptr = boardptr->next_on_interrupt) 2365 { 2366 /* write to the MIC csr to reset the PCI interrupt */ 2367 writeb(0, (unsigned char*)(boardptr->MICCMD_REG + MICCMD_MICCSR)); 2368 2369 /* now, write to the CIM interrupt ena to re-enable interrupt generation */ 2370 writeb(0, (unsigned char*)(boardptr->CIMCMD_REG + CIMCMD_WRINTENA)); 2371 2372 /* now, activate PCI interrupts */ 2373 writel(AMCC_AOINTPINENA, (unsigned int*)(boardptr->AMCC_REG + AMCC_INTCSR)); 2374 } 2375 } 2376 else 2377 { 2378 printk(KERN_ALERT "Unable to get interrupt, board set up not complete %i.\n", intr_val); 2379 } 2380 } 2381 } 2382 2383 /* all done! a lot of work */ 2384 2385#if !defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0)) 2386 return -1; /* otherwise 2.2 probe uses up 2387 * a default device structure*/ 2388#else 2389 return 0; 2390#endif 2391} 2392 2393#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0) 2394#ifdef MODULE 2395/* cleanup module/free up virtual memory */ 2396/* space*/ 2397void cleanup_module(void) 2398#endif 2399#else 2400void auraXX20_cleanup(void) 2401#endif 2402{ 2403 SAB_BOARD *boardptr; 2404 SAB_CHIP *chipptr; 2405 SAB_PORT *portptr; 2406 AURA_CIM *cimptr; 2407 int intr_val; 2408 extern void sab8253x_cleanup_ttydriver(void); 2409 2410 printk(KERN_ALERT "auraXX20n: unloading AURAXX20 driver.\n"); 2411 2412 sab8253x_cleanup_ttydriver(); /* clean up tty */ 2413 2414 /* unallocate and turn off ints */ 2415 for(intr_val = 0; intr_val < NUMINTS; ++intr_val) 2416 { 2417 if((AuraBoardESCC2IrqRoot[intr_val] != NULL) || (AuraBoardESCC8IrqRoot[intr_val] != NULL) || 2418 (AuraBoardMCSIrqRoot[intr_val] != NULL)) 2419 { 2420 for(boardptr = AuraBoardESCC2IrqRoot[intr_val]; boardptr != NULL; 2421 boardptr = boardptr->next_on_interrupt) 2422 { 2423 writel(PLX_INT_OFF, &(boardptr->b_bridge->intr)); 2424 } 2425 for(boardptr = AuraBoardESCC8IrqRoot[intr_val]; boardptr != NULL; 2426 boardptr = boardptr->next_on_interrupt) 2427 { 2428 writel(PLX_INT_OFF, &(boardptr->b_bridge->intr)); 2429 } 2430 for(boardptr = AuraBoardMCSIrqRoot[intr_val]; boardptr != NULL; 2431 boardptr = boardptr->next_on_interrupt) 2432 { 2433 writel(AMCC_INT_OFF, (unsigned int*)(boardptr->AMCC_REG + AMCC_INTCSR)); 2434 (void) wanmcs_reset(boardptr); 2435 writel(AMCC_INT_OFF, (unsigned int*)(boardptr->AMCC_REG + AMCC_INTCSR)); 2436 } 2437 2438 free_irq(intr_val, &AuraBoardESCC2IrqRoot[intr_val]); /* free up board int 2439 * note that if two boards 2440 * share an int, two int 2441 * handlers were registered 2442 * 2443 */ 2444 } 2445 } 2446 2447 /* disable chips and free board memory*/ 2448 while(AuraBoardRoot) 2449 { 2450 boardptr = AuraBoardRoot; 2451 for(chipptr = boardptr->board_chipbase; chipptr != NULL; chipptr = chipptr->next_by_board) 2452 { 2453 (*chipptr->int_disable)(chipptr); /* make sure no ints can come int */ 2454 } 2455 AuraBoardRoot = boardptr->nextboard; 2456 if(boardptr->b_type == BD_WANMCS) 2457 { 2458 if(boardptr->virtbaseaddress0 != 0) 2459 { 2460 DEBUGPRINT((KERN_ALERT "auraXX20n: unmapping virtual address %p.\n", 2461 (void*)boardptr->virtbaseaddress0)); 2462 iounmap((void*)boardptr->virtbaseaddress0); 2463 boardptr->virtbaseaddress0 = 0; 2464 } 2465 2466 if(boardptr->virtbaseaddress1 != 0) 2467 { 2468 DEBUGPRINT((KERN_ALERT "auraXX20n: unmapping virtual address %p.\n", 2469 (void*)boardptr->virtbaseaddress1)); 2470 iounmap((void*)boardptr->virtbaseaddress1); 2471 boardptr->virtbaseaddress1 = 0; 2472 } 2473 2474 if(boardptr->virtbaseaddress2 != 0) 2475 { 2476 DEBUGPRINT((KERN_ALERT "auraXX20n: unmapping virtual address %p.\n", 2477 (void*)boardptr->virtbaseaddress2)); 2478 iounmap((void*)boardptr->virtbaseaddress2); 2479 boardptr->virtbaseaddress2 = 0; 2480 } 2481 2482 if(boardptr->virtbaseaddress3 != 0) 2483 { 2484 DEBUGPRINT((KERN_ALERT "auraXX20n: unmapping virtual address %p.\n", 2485 (void*)boardptr->virtbaseaddress3)); 2486 iounmap((void*)boardptr->virtbaseaddress3); 2487 boardptr->virtbaseaddress3 = 0; 2488 } 2489 2490 } 2491 else /* everything but wan multichannel servers */ 2492 { 2493 if(boardptr->virtbaseaddress0) 2494 { 2495 DEBUGPRINT((KERN_ALERT 2496 "auraXX20n: unmapping virtual address %p.\n", 2497 (void*)boardptr->virtbaseaddress0)); 2498 iounmap((void*)boardptr->virtbaseaddress0); 2499 boardptr->virtbaseaddress0 = 0; 2500 } 2501 if(boardptr->virtbaseaddress2) 2502 { 2503 DEBUGPRINT((KERN_ALERT 2504 "auraXX20n: unmapping virtual address %p.\n", 2505 (void*)boardptr->virtbaseaddress2)); 2506 iounmap((void*)boardptr->virtbaseaddress2); 2507 boardptr->virtbaseaddress2 = 0; 2508 } 2509 } 2510 kfree(boardptr); 2511 } 2512 2513 while(AuraCimRoot) 2514 { 2515 cimptr = AuraCimRoot; 2516 AuraCimRoot = cimptr->next; 2517 kfree(cimptr); 2518 } 2519 2520 2521 while(AuraChipRoot) /* free chip memory */ 2522 { 2523 chipptr = AuraChipRoot; 2524 AuraChipRoot = chipptr->next; 2525 kfree(chipptr); 2526 } 2527 2528 if(sab8253xc_name && (sab8253xc_major > 0)) /* unregister the chr device */ 2529 { 2530 unregister_chrdev(sab8253xc_major, sab8253xc_name); 2531 } 2532 2533 while(Sab8253xRoot) /* free up network stuff */ 2534 { 2535 SAB_PORT *priv; 2536 priv = (SAB_PORT *)Sab8253xRoot->priv; 2537 unregister_netdev(Sab8253xRoot); 2538#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0) 2539 kfree(Sab8253xRoot.name); 2540#endif 2541 kfree(Sab8253xRoot); 2542 Sab8253xRoot = priv->next_dev; 2543 } 2544 2545 while(AuraPortRoot) /* free up port memory */ 2546 { 2547 portptr = AuraPortRoot; 2548 AuraPortRoot = portptr->next; 2549 if(portptr->dcontrol2.receive) 2550 { 2551 kfree(portptr->dcontrol2.receive); 2552 } 2553 if(portptr->dcontrol2.transmit) 2554 { 2555 kfree(portptr->dcontrol2.transmit); 2556 } 2557 kfree(portptr); 2558 } 2559} 2560 2561/* 2562 * Hardware dependent read and write functions. 2563 * We have functions to write/read a byte, write/read 2564 * a word and read and write the FIFO 2565 */ 2566 2567 2568/*************************************************************************** 2569 * aura_readb: Function to read a byte on a 4X20P, 8X20P or Sun serial 2570 * 2571 * 2572 * Parameters : 2573 * port: The port being accessed 2574 * reg: The address of the register 2575 * 2576 * Return value : The value of the register. 2577 * 2578 * Prerequisite : The port must have been opened 2579 * 2580 * Remark : 2581 * 2582 * Author : fw 2583 * 2584 * Revision : Oct 10 2000, creation 2585 ***************************************************************************/ 2586 2587static unsigned char aura_readb(struct sab_port *port, unsigned char *reg) 2588{ 2589 return readb(reg); 2590} 2591 2592/*************************************************************************** 2593 * aura_writeb: Function to write a byte on a 4X20P, 8X20P or Sun serial 2594 * 2595 * 2596 * Parameters : 2597 * port: The port being accessed 2598 * reg: The address of the register 2599 * val: The value to put into the register 2600 * 2601 * Return value : None 2602 * 2603 * Prerequisite : The port must have been opened 2604 * 2605 * Remark : 2606 * 2607 * Author : fw 2608 * 2609 * Revision : Oct 10 2000, creation 2610 ***************************************************************************/ 2611 2612static void aura_writeb(struct sab_port *port, unsigned char *reg,unsigned char val) 2613{ 2614 writeb(val,reg); 2615} 2616 2617/*************************************************************************** 2618 * aura_readw: Function to read a word on a 4X20P, 8X20P or Sun serial 2619 * 2620 * 2621 * Parameters : 2622 * port: The port being accessed 2623 * reg: The address of the hw memory to access 2624 * 2625 * Return value : The value of the memory area. 2626 * 2627 * Prerequisite : The port must have been opened 2628 * 2629 * Remark : 2630 * 2631 * Author : fw 2632 * 2633 * Revision : Oct 10 2000, creation 2634 ***************************************************************************/ 2635static unsigned short aura_readw(struct sab_port *port, unsigned short *reg) 2636{ 2637 return readw(reg); 2638} 2639 2640/*************************************************************************** 2641 * aura_writew: Function to write a word on a 4X20P, 8X20P or Sun serial 2642 * 2643 * 2644 * Parameters : 2645 * port: The port being accessed 2646 * reg: The address of the hw memory to access 2647 * val: The value to put into the register 2648 * 2649 * Return value : The value of the memory area. 2650 * 2651 * Prerequisite : The port must have been opened 2652 * 2653 * Remark : 2654 * 2655 * Author : fw 2656 * 2657 * Revision : Oct 10 2000, creation 2658 ***************************************************************************/ 2659 2660static void aura_writew(struct sab_port *port, unsigned short *reg,unsigned short val) 2661{ 2662 writew(val,reg); 2663} 2664 2665/*************************************************************************** 2666 * aura_readfifo: Function to read the FIFO on a 4X20P, 8X20P or Sun serial 2667 * 2668 * 2669 * Parameters : 2670 * port: The port being accessed 2671 * buf: The address of a buffer where we should put 2672 * what we read 2673 * nbytes: How many chars to read. 2674 * 2675 * Return value : none 2676 * 2677 * Prerequisite : The port must have been opened 2678 * 2679 * Remark : 2680 * 2681 * Author : fw 2682 * 2683 * Revision : Oct 13 2000, creation 2684 ***************************************************************************/ 2685static void aura_readfifo(struct sab_port *port, unsigned char *buf, unsigned int nbytes) 2686{ 2687 int i; 2688 unsigned short *wptr = (unsigned short*) buf; 2689 int nwords = ((nbytes+1)/2); 2690 for(i = 0; i < nwords; i ++) 2691 { 2692 wptr[i] = readw(((unsigned short *)port->regs)); 2693 } 2694} 2695 2696/*************************************************************************** 2697 * aura_writefifo: Function to write the FIFO on a 4X20P, 8X20P or Sun serial 2698 * 2699 * 2700 * Parameters : 2701 * port: The port being accessed 2702 * 2703 * Return value : none 2704 * 2705 * Prerequisite : The port must have been opened 2706 * 2707 * Remark : 2708 * 2709 * Author : fw 2710 * 2711 * Revision : Oct 13 2000, creation 2712 ***************************************************************************/ 2713static void aura_writefifo(struct sab_port *port) 2714{ 2715 int i,max,maxw; 2716 unsigned short *wptr; 2717 unsigned char buffer[32]; 2718 2719 if(port->xmit_cnt <= 0) 2720 { 2721 return; 2722 } 2723 max= (port->xmit_fifo_size < port->xmit_cnt) ? port->xmit_fifo_size : port->xmit_cnt; 2724 2725 for (i = 0; i < max; i++) 2726 { 2727 buffer[i] = port->xmit_buf[port->xmit_tail++]; 2728 port->xmit_tail &= (SAB8253X_XMIT_SIZE - 1); 2729 port->icount.tx++; 2730 port->xmit_cnt--; 2731 } 2732 2733 maxw = max/2; 2734 wptr = (unsigned short*) buffer; 2735 2736 for(i = 0; i < maxw; ++i) 2737 { 2738 writew(wptr[i], (unsigned short *)port->regs); 2739 } 2740 2741 if(max & 1) 2742 { 2743 writeb(buffer[max-1], (unsigned char*)port->regs); 2744 } 2745} 2746 2747/*************************************************************************** 2748 * wmsaura_readb: Function to read a byte on a LMS, WMS 2749 * 2750 * 2751 * Parameters : 2752 * port: The port being accessed 2753 * reg: The address of the register 2754 * 2755 * Return value : The value of the register. 2756 * 2757 * Prerequisite : The port must have been opened 2758 * 2759 * Remark : TO BE IMPLEMENTED 2760 * 2761 * Author : fw 2762 * 2763 * Revision : Oct 10 2000, creation 2764 ***************************************************************************/ 2765 2766static unsigned char wmsaura_readb(struct sab_port *port, unsigned char *reg) 2767{ 2768 return readb((unsigned char*) (((unsigned int) reg) + CIMCMD_RDREGB)); 2769} 2770 2771/*************************************************************************** 2772 * wmsaura_writeb: Function to write a byte on a LMS, WMS 2773 * 2774 * 2775 * Parameters : 2776 * port: The port being accessed 2777 * reg: The address of the register 2778 * val: The value to put into the register 2779 * 2780 * Return value : None 2781 * 2782 * Prerequisite : The port must have been opened 2783 * 2784 * Remark : TO BE IMPLEMENTED 2785 * 2786 * Author : fw 2787 * 2788 * Revision : Oct 10 2000, creation 2789 ***************************************************************************/ 2790 2791static void wmsaura_writeb(struct sab_port *port, unsigned char *reg,unsigned char val) 2792{ 2793 writeb(val, (unsigned char*) (((unsigned int) reg) + CIMCMD_WRREGB)); 2794} 2795 2796/*************************************************************************** 2797 * wmsaura_readw: Function to read a word on a LMS, WMS 2798 * 2799 * 2800 * Parameters : 2801 * port: The port being accessed 2802 * reg: The address of the hw memory to access 2803 * 2804 * Return value : The value of the memory area. 2805 * 2806 * Prerequisite : The port must have been opened 2807 * 2808 * Remark : TO BE IMPLEMENTED 2809 * 2810 * Author : fw 2811 * 2812 * Revision : Oct 10 2000, creation 2813 ***************************************************************************/ 2814static unsigned short wmsaura_readw(struct sab_port *port, unsigned short *reg) 2815{ 2816 unsigned short readval; 2817 unsigned int address; 2818 address = (unsigned int) reg; 2819 2820 readval = readb((unsigned char*) (address + CIMCMD_RDREGB)); 2821 ++address; 2822 return (readval | (readb((unsigned char*) (address + CIMCMD_RDREGB)) << 8)); 2823} 2824 2825/*************************************************************************** 2826 * wmsaura_writew: Function to write a word on a LMS, WMS 2827 * 2828 * 2829 * Parameters : 2830 * port: The port being accessed 2831 * reg: The address of the hw memory to access 2832 * val: The value to put into the register 2833 * 2834 * Return value : The value of the memory area. 2835 * 2836 * Prerequisite : The port must have been opened 2837 * 2838 * Remark : TO BE IMPLEMENTED 2839 * 2840 * Author : fw 2841 * 2842 * Revision : Oct 10 2000, creation 2843 ***************************************************************************/ 2844 2845static void wmsaura_writew(struct sab_port *port, unsigned short *reg, unsigned short val) 2846{ 2847 unsigned char vallow; 2848 unsigned char valhigh; 2849 unsigned int address; 2850 2851 address = (unsigned int) reg; 2852 2853 vallow = (unsigned char) val; 2854 valhigh = (unsigned char) (val >> 8); 2855 2856 writeb(vallow, (unsigned char*) (address + CIMCMD_WRREGB)); 2857 ++address; 2858 writeb(valhigh, (unsigned char*) (address + CIMCMD_WRREGB)); 2859} 2860 2861static void wmsaura_readfifo(struct sab_port *port, unsigned char *buf, unsigned int nbytes) 2862{ 2863#ifdef FIFO_DIRECT 2864 unsigned short fifo[32/2]; /* this array is word aligned 2865 * buf may not be word aligned*/ 2866 unsigned int nwords; 2867 int i; 2868 int wcount; 2869 unsigned int address; 2870 2871 if (nbytes == 0) 2872 { 2873 return; 2874 } 2875 2876 wcount = ((nbytes + 1) >> 1); 2877 /* Read the thing into the local FIFO and copy it out. */ 2878 address = (unsigned int) port->regs; 2879 2880 for(i = 0; i < wcount; ++i) 2881 { 2882 fifo[i] = readw((unsigned short*)(address + CIMCMD_RDFIFOW)); 2883 } 2884 2885 memcpy((unsigned char*) buf, (unsigned char*) &(fifo[0]), (unsigned int) nbytes); 2886 2887#else /* FIFO_DIRECT */ 2888 unsigned short fifo[32/2]; 2889 int i; 2890 int wcount; 2891 SAB_BOARD *bptr; 2892 unsigned int channel; 2893 2894 if (nbytes == 0) 2895 { 2896 return; 2897 } 2898 2899 bptr = port->board; 2900 wcount = ((nbytes + 1) >> 1); 2901 channel = (((unsigned char*) port->regs) - bptr->CIMCMD_REG); /* should be properly shifted */ 2902 2903 /* 2904 * Trigger a cache read by writing the nwords - 1 to the 2905 * magic place. 2906 */ 2907 2908 writeb((unsigned char) wcount, bptr->MICCMD_REG + (MICCMD_CACHETRIG + channel)); 2909 2910 /* 2911 * Now, read out the contents. 2912 */ 2913 2914 channel >>= 1; 2915 2916 for(i = 0; i < wcount; ++i) 2917 { 2918 fifo[i] = readw((unsigned short*)(bptr->FIFOCACHE_REG + (channel + (i << 1)))); 2919 } 2920 2921 memcpy((unsigned char*) buf, (unsigned char*) &(fifo[0]), (unsigned int) nbytes); 2922#endif /* !FIFO_DIRECT */ 2923} 2924 2925static void wmsaura_writefifo(struct sab_port *port) 2926{ 2927 unsigned short fifo[32/2]; 2928 unsigned char* fifob = (unsigned char*) fifo; 2929 int i,max; 2930 int wcount; 2931 unsigned int address; 2932 2933 if(port->xmit_cnt <= 0) 2934 { 2935 return; 2936 } 2937 max = (port->xmit_fifo_size < port->xmit_cnt) ? port->xmit_fifo_size:port->xmit_cnt; 2938 for (i = 0; i < max; i++) 2939 { 2940 fifob[i] = port->xmit_buf[port->xmit_tail++]; 2941 port->xmit_tail &= (SAB8253X_XMIT_SIZE - 1); 2942 port->icount.tx++; 2943 port->xmit_cnt--; 2944 } 2945 2946 wcount = (max >> 1); 2947 /* Copy from the linear local FIFO into the hardware fifo. */ 2948 address = (unsigned int) port->regs; 2949 2950 for(i = 0; i < wcount; ++i) 2951 { 2952 writew(fifo[i], (unsigned short*)(address + CIMCMD_WRFIFOW)); 2953 } 2954 if(max & 1) /* odd byte */ 2955 { 2956 --max; 2957 writeb(fifob[max], (unsigned short*)(address + CIMCMD_WRFIFOB)); 2958 } 2959} 2960 2961module_init(auraXX20_probe); 2962module_exit(auraXX20_cleanup); 2963MODULE_DESCRIPTION("Aurora Multiport Multiprotocol Serial Driver"); 2964MODULE_AUTHOR("Joachim Martillo <martillo@telfordtools.com>"); 2965