Searched hist:281438 (Results 1 - 22 of 22) sorted by relevance
| /freebsd-11.0-release/sys/dev/uart/ | ||
| H A D | uart_dev_msm.c | diff 281438 Sat Apr 11 17:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| H A D | uart_dev_quicc.c | diff 281438 Sat Apr 11 17:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| H A D | uart_dev_ti8250.c | diff 281438 Sat Apr 11 17:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| H A D | uart_dev_imx.c | diff 281438 Sat Apr 11 17:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| H A D | uart_dev_lpc.c | diff 281438 Sat Apr 11 17:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| H A D | uart_dev_pl011.c | diff 281438 Sat Apr 11 17:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| H A D | uart_cpu.h | diff 281438 Sat Apr 11 17:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| H A D | uart_cpu_fdt.c | diff 281438 Sat Apr 11 17:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| H A D | uart_dev_sab82532.c | diff 281438 Sat Apr 11 17:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| H A D | uart_bus.h | diff 281438 Sat Apr 11 17:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| H A D | uart_bus_fdt.c | diff 281438 Sat Apr 11 17:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| H A D | uart_dev_z8530.c | diff 281438 Sat Apr 11 17:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| H A D | uart_core.c | diff 281438 Sat Apr 11 17:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| H A D | uart_dev_ns8250.c | diff 281438 Sat Apr 11 17:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| /freebsd-11.0-release/sys/arm/samsung/exynos/ | ||
| H A D | exynos_uart.c | diff 281438 Sat Apr 11 17:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| /freebsd-11.0-release/sys/arm/amlogic/aml8726/ | ||
| H A D | uart_dev_aml8726.c | diff 281438 Sat Apr 11 17:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| /freebsd-11.0-release/sys/arm/freescale/vybrid/ | ||
| H A D | vf_uart.c | diff 281438 Sat Apr 11 17:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| /freebsd-11.0-release/sys/mips/adm5120/ | ||
| H A D | uart_dev_adm5120.c | diff 281438 Sat Apr 11 17:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| /freebsd-11.0-release/sys/mips/rt305x/ | ||
| H A D | uart_dev_rt305x.c | diff 281438 Sat Apr 11 17:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| /freebsd-11.0-release/sys/mips/atheros/ | ||
| H A D | uart_dev_ar933x.c | diff 281438 Sat Apr 11 17:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| /freebsd-11.0-release/sys/sparc64/pci/ | ||
| H A D | sbbc.c | diff 281438 Sat Apr 11 17:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| /freebsd-11.0-release/sys/mips/cavium/ | ||
| H A D | uart_dev_oct16550.c | diff 281438 Sat Apr 11 17:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
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