1/*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include "opt_platform.h" 28#include "opt_uart.h" 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: releng/11.0/sys/dev/uart/uart_dev_ns8250.c 298955 2016-05-03 03:41:25Z pfg $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/conf.h> 37#include <sys/kernel.h> 38#include <sys/sysctl.h> 39#include <machine/bus.h> 40 41#ifdef FDT 42#include <dev/fdt/fdt_common.h> 43#include <dev/ofw/ofw_bus.h> 44#include <dev/ofw/ofw_bus_subr.h> 45#endif 46 47#include <dev/uart/uart.h> 48#include <dev/uart/uart_cpu.h> 49#ifdef FDT 50#include <dev/uart/uart_cpu_fdt.h> 51#endif 52#include <dev/uart/uart_bus.h> 53#include <dev/uart/uart_dev_ns8250.h> 54#include <dev/uart/uart_ppstypes.h> 55 56#include <dev/ic/ns16550.h> 57 58#include "uart_if.h" 59 60#define DEFAULT_RCLK 1843200 61 62/* 63 * Set the default baudrate tolerance to 3.0%. 64 * 65 * Some embedded boards have odd reference clocks (eg 25MHz) 66 * and we need to handle higher variances in the target baud rate. 67 */ 68#ifndef UART_DEV_TOLERANCE_PCT 69#define UART_DEV_TOLERANCE_PCT 30 70#endif /* UART_DEV_TOLERANCE_PCT */ 71 72static int broken_txfifo = 0; 73SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 74 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 75 76/* 77 * Clear pending interrupts. THRE is cleared by reading IIR. Data 78 * that may have been received gets lost here. 79 */ 80static void 81ns8250_clrint(struct uart_bas *bas) 82{ 83 uint8_t iir, lsr; 84 85 iir = uart_getreg(bas, REG_IIR); 86 while ((iir & IIR_NOPEND) == 0) { 87 iir &= IIR_IMASK; 88 if (iir == IIR_RLS) { 89 lsr = uart_getreg(bas, REG_LSR); 90 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 91 (void)uart_getreg(bas, REG_DATA); 92 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 93 (void)uart_getreg(bas, REG_DATA); 94 else if (iir == IIR_MLSC) 95 (void)uart_getreg(bas, REG_MSR); 96 uart_barrier(bas); 97 iir = uart_getreg(bas, REG_IIR); 98 } 99} 100 101static int 102ns8250_delay(struct uart_bas *bas) 103{ 104 int divisor; 105 u_char lcr; 106 107 lcr = uart_getreg(bas, REG_LCR); 108 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 109 uart_barrier(bas); 110 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 111 uart_barrier(bas); 112 uart_setreg(bas, REG_LCR, lcr); 113 uart_barrier(bas); 114 115 /* 1/10th the time to transmit 1 character (estimate). */ 116 if (divisor <= 134) 117 return (16000000 * divisor / bas->rclk); 118 return (16000 * divisor / (bas->rclk / 1000)); 119} 120 121static int 122ns8250_divisor(int rclk, int baudrate) 123{ 124 int actual_baud, divisor; 125 int error; 126 127 if (baudrate == 0) 128 return (0); 129 130 divisor = (rclk / (baudrate << 3) + 1) >> 1; 131 if (divisor == 0 || divisor >= 65536) 132 return (0); 133 actual_baud = rclk / (divisor << 4); 134 135 /* 10 times error in percent: */ 136 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 137 138 /* enforce maximum error tolerance: */ 139 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 140 return (0); 141 142 return (divisor); 143} 144 145static int 146ns8250_drain(struct uart_bas *bas, int what) 147{ 148 int delay, limit; 149 150 delay = ns8250_delay(bas); 151 152 if (what & UART_DRAIN_TRANSMITTER) { 153 /* 154 * Pick an arbitrary high limit to avoid getting stuck in 155 * an infinite loop when the hardware is broken. Make the 156 * limit high enough to handle large FIFOs. 157 */ 158 limit = 10*1024; 159 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 160 DELAY(delay); 161 if (limit == 0) { 162 /* printf("ns8250: transmitter appears stuck... "); */ 163 return (EIO); 164 } 165 } 166 167 if (what & UART_DRAIN_RECEIVER) { 168 /* 169 * Pick an arbitrary high limit to avoid getting stuck in 170 * an infinite loop when the hardware is broken. Make the 171 * limit high enough to handle large FIFOs and integrated 172 * UARTs. The HP rx2600 for example has 3 UARTs on the 173 * management board that tend to get a lot of data send 174 * to it when the UART is first activated. 175 */ 176 limit=10*4096; 177 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 178 (void)uart_getreg(bas, REG_DATA); 179 uart_barrier(bas); 180 DELAY(delay << 2); 181 } 182 if (limit == 0) { 183 /* printf("ns8250: receiver appears broken... "); */ 184 return (EIO); 185 } 186 } 187 188 return (0); 189} 190 191/* 192 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 193 * drained. WARNING: this function clobbers the FIFO setting! 194 */ 195static void 196ns8250_flush(struct uart_bas *bas, int what) 197{ 198 uint8_t fcr; 199 200 fcr = FCR_ENABLE; 201 if (what & UART_FLUSH_TRANSMITTER) 202 fcr |= FCR_XMT_RST; 203 if (what & UART_FLUSH_RECEIVER) 204 fcr |= FCR_RCV_RST; 205 uart_setreg(bas, REG_FCR, fcr); 206 uart_barrier(bas); 207} 208 209static int 210ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 211 int parity) 212{ 213 int divisor; 214 uint8_t lcr; 215 216 lcr = 0; 217 if (databits >= 8) 218 lcr |= LCR_8BITS; 219 else if (databits == 7) 220 lcr |= LCR_7BITS; 221 else if (databits == 6) 222 lcr |= LCR_6BITS; 223 else 224 lcr |= LCR_5BITS; 225 if (stopbits > 1) 226 lcr |= LCR_STOPB; 227 lcr |= parity << 3; 228 229 /* Set baudrate. */ 230 if (baudrate > 0) { 231 divisor = ns8250_divisor(bas->rclk, baudrate); 232 if (divisor == 0) 233 return (EINVAL); 234 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 235 uart_barrier(bas); 236 uart_setreg(bas, REG_DLL, divisor & 0xff); 237 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 238 uart_barrier(bas); 239 } 240 241 /* Set LCR and clear DLAB. */ 242 uart_setreg(bas, REG_LCR, lcr); 243 uart_barrier(bas); 244 return (0); 245} 246 247/* 248 * Low-level UART interface. 249 */ 250static int ns8250_probe(struct uart_bas *bas); 251static void ns8250_init(struct uart_bas *bas, int, int, int, int); 252static void ns8250_term(struct uart_bas *bas); 253static void ns8250_putc(struct uart_bas *bas, int); 254static int ns8250_rxready(struct uart_bas *bas); 255static int ns8250_getc(struct uart_bas *bas, struct mtx *); 256 257struct uart_ops uart_ns8250_ops = { 258 .probe = ns8250_probe, 259 .init = ns8250_init, 260 .term = ns8250_term, 261 .putc = ns8250_putc, 262 .rxready = ns8250_rxready, 263 .getc = ns8250_getc, 264}; 265 266static int 267ns8250_probe(struct uart_bas *bas) 268{ 269 u_char val; 270 271 /* Check known 0 bits that don't depend on DLAB. */ 272 val = uart_getreg(bas, REG_IIR); 273 if (val & 0x30) 274 return (ENXIO); 275 /* 276 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 277 * chip, but otherwise doesn't seem to have a function. In 278 * other words, uart(4) works regardless. Ignore that bit so 279 * the probe succeeds. 280 */ 281 val = uart_getreg(bas, REG_MCR); 282 if (val & 0xa0) 283 return (ENXIO); 284 285 return (0); 286} 287 288static void 289ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 290 int parity) 291{ 292 u_char ier; 293 294 if (bas->rclk == 0) 295 bas->rclk = DEFAULT_RCLK; 296 ns8250_param(bas, baudrate, databits, stopbits, parity); 297 298 /* Disable all interrupt sources. */ 299 /* 300 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 301 * UARTs split the receive time-out interrupt bit out separately as 302 * 0x10. This gets handled by ier_mask and ier_rxbits below. 303 */ 304 ier = uart_getreg(bas, REG_IER) & 0xe0; 305 uart_setreg(bas, REG_IER, ier); 306 uart_barrier(bas); 307 308 /* Disable the FIFO (if present). */ 309 uart_setreg(bas, REG_FCR, 0); 310 uart_barrier(bas); 311 312 /* Set RTS & DTR. */ 313 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 314 uart_barrier(bas); 315 316 ns8250_clrint(bas); 317} 318 319static void 320ns8250_term(struct uart_bas *bas) 321{ 322 323 /* Clear RTS & DTR. */ 324 uart_setreg(bas, REG_MCR, MCR_IE); 325 uart_barrier(bas); 326} 327 328static void 329ns8250_putc(struct uart_bas *bas, int c) 330{ 331 int limit; 332 333 limit = 250000; 334 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 335 DELAY(4); 336 uart_setreg(bas, REG_DATA, c); 337 uart_barrier(bas); 338 limit = 250000; 339 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 340 DELAY(4); 341} 342 343static int 344ns8250_rxready(struct uart_bas *bas) 345{ 346 347 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 348} 349 350static int 351ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 352{ 353 int c; 354 355 uart_lock(hwmtx); 356 357 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 358 uart_unlock(hwmtx); 359 DELAY(4); 360 uart_lock(hwmtx); 361 } 362 363 c = uart_getreg(bas, REG_DATA); 364 365 uart_unlock(hwmtx); 366 367 return (c); 368} 369 370static kobj_method_t ns8250_methods[] = { 371 KOBJMETHOD(uart_attach, ns8250_bus_attach), 372 KOBJMETHOD(uart_detach, ns8250_bus_detach), 373 KOBJMETHOD(uart_flush, ns8250_bus_flush), 374 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 375 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 376 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 377 KOBJMETHOD(uart_param, ns8250_bus_param), 378 KOBJMETHOD(uart_probe, ns8250_bus_probe), 379 KOBJMETHOD(uart_receive, ns8250_bus_receive), 380 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 381 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 382 KOBJMETHOD(uart_grab, ns8250_bus_grab), 383 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 384 { 0, 0 } 385}; 386 387struct uart_class uart_ns8250_class = { 388 "ns8250", 389 ns8250_methods, 390 sizeof(struct ns8250_softc), 391 .uc_ops = &uart_ns8250_ops, 392 .uc_range = 8, 393 .uc_rclk = DEFAULT_RCLK, 394 .uc_rshift = 0 395}; 396 397#ifdef FDT 398static struct ofw_compat_data compat_data[] = { 399 {"ns16550", (uintptr_t)&uart_ns8250_class}, 400 {"ns16550a", (uintptr_t)&uart_ns8250_class}, 401 {NULL, (uintptr_t)NULL}, 402}; 403UART_FDT_CLASS_AND_DEVICE(compat_data); 404#endif 405 406/* Use token-pasting to form SER_ and MSR_ named constants. */ 407#define SER(sig) SER_##sig 408#define SERD(sig) SER_D##sig 409#define MSR(sig) MSR_##sig 410#define MSRD(sig) MSR_D##sig 411 412/* 413 * Detect signal changes using software delta detection. The previous state of 414 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 415 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 416 * new state of both the signal and the delta bits. 417 */ 418#define SIGCHGSW(var, msr, sig) \ 419 if ((msr) & MSR(sig)) { \ 420 if ((var & SER(sig)) == 0) \ 421 var |= SERD(sig) | SER(sig); \ 422 } else { \ 423 if ((var & SER(sig)) != 0) \ 424 var = SERD(sig) | (var & ~SER(sig)); \ 425 } 426 427/* 428 * Detect signal changes using the hardware msr delta bits. This is currently 429 * used only when PPS timing information is being captured using the "narrow 430 * pulse" option. With a narrow PPS pulse the signal may not still be asserted 431 * by time the interrupt handler is invoked. The hardware will latch the fact 432 * that it changed in the delta bits. 433 */ 434#define SIGCHGHW(var, msr, sig) \ 435 if ((msr) & MSRD(sig)) { \ 436 if (((msr) & MSR(sig)) != 0) \ 437 var |= SERD(sig) | SER(sig); \ 438 else \ 439 var = SERD(sig) | (var & ~SER(sig)); \ 440 } 441 442int 443ns8250_bus_attach(struct uart_softc *sc) 444{ 445 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 446 struct uart_bas *bas; 447 unsigned int ivar; 448#ifdef FDT 449 phandle_t node; 450 pcell_t cell; 451#endif 452 453#ifdef FDT 454 /* Check whether uart has a broken txfifo. */ 455 node = ofw_bus_get_node(sc->sc_dev); 456 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 457 broken_txfifo = cell ? 1 : 0; 458#endif 459 460 bas = &sc->sc_bas; 461 462 ns8250->mcr = uart_getreg(bas, REG_MCR); 463 ns8250->fcr = FCR_ENABLE; 464 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 465 &ivar)) { 466 if (UART_FLAGS_FCR_RX_LOW(ivar)) 467 ns8250->fcr |= FCR_RX_LOW; 468 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 469 ns8250->fcr |= FCR_RX_MEDL; 470 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 471 ns8250->fcr |= FCR_RX_HIGH; 472 else 473 ns8250->fcr |= FCR_RX_MEDH; 474 } else 475 ns8250->fcr |= FCR_RX_MEDH; 476 477 /* Get IER mask */ 478 ivar = 0xf0; 479 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 480 &ivar); 481 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 482 483 /* Get IER RX interrupt bits */ 484 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 485 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 486 &ivar); 487 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 488 489 uart_setreg(bas, REG_FCR, ns8250->fcr); 490 uart_barrier(bas); 491 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 492 493 if (ns8250->mcr & MCR_DTR) 494 sc->sc_hwsig |= SER_DTR; 495 if (ns8250->mcr & MCR_RTS) 496 sc->sc_hwsig |= SER_RTS; 497 ns8250_bus_getsig(sc); 498 499 ns8250_clrint(bas); 500 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 501 ns8250->ier |= ns8250->ier_rxbits; 502 uart_setreg(bas, REG_IER, ns8250->ier); 503 uart_barrier(bas); 504 505 /* 506 * Timing of the H/W access was changed with r253161 of uart_core.c 507 * It has been observed that an ITE IT8513E would signal a break 508 * condition with pretty much every character it received, unless 509 * it had enough time to settle between ns8250_bus_attach() and 510 * ns8250_bus_ipend() -- which it accidentally had before r253161. 511 * It's not understood why the UART chip behaves this way and it 512 * could very well be that the DELAY make the H/W work in the same 513 * accidental manner as before. More analysis is warranted, but 514 * at least now we fixed a known regression. 515 */ 516 DELAY(200); 517 return (0); 518} 519 520int 521ns8250_bus_detach(struct uart_softc *sc) 522{ 523 struct ns8250_softc *ns8250; 524 struct uart_bas *bas; 525 u_char ier; 526 527 ns8250 = (struct ns8250_softc *)sc; 528 bas = &sc->sc_bas; 529 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 530 uart_setreg(bas, REG_IER, ier); 531 uart_barrier(bas); 532 ns8250_clrint(bas); 533 return (0); 534} 535 536int 537ns8250_bus_flush(struct uart_softc *sc, int what) 538{ 539 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 540 struct uart_bas *bas; 541 int error; 542 543 bas = &sc->sc_bas; 544 uart_lock(sc->sc_hwmtx); 545 if (sc->sc_rxfifosz > 1) { 546 ns8250_flush(bas, what); 547 uart_setreg(bas, REG_FCR, ns8250->fcr); 548 uart_barrier(bas); 549 error = 0; 550 } else 551 error = ns8250_drain(bas, what); 552 uart_unlock(sc->sc_hwmtx); 553 return (error); 554} 555 556int 557ns8250_bus_getsig(struct uart_softc *sc) 558{ 559 uint32_t old, sig; 560 uint8_t msr; 561 562 /* 563 * The delta bits are reputed to be broken on some hardware, so use 564 * software delta detection by default. Use the hardware delta bits 565 * when capturing PPS pulses which are too narrow for software detection 566 * to see the edges. Hardware delta for RI doesn't work like the 567 * others, so always use software for it. Other threads may be changing 568 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully 569 * update without other changes happening. Note that the SIGCHGxx() 570 * macros carefully preserve the delta bits when we have to loop several 571 * times and a signal transitions between iterations. 572 */ 573 do { 574 old = sc->sc_hwsig; 575 sig = old; 576 uart_lock(sc->sc_hwmtx); 577 msr = uart_getreg(&sc->sc_bas, REG_MSR); 578 uart_unlock(sc->sc_hwmtx); 579 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 580 SIGCHGHW(sig, msr, DSR); 581 SIGCHGHW(sig, msr, CTS); 582 SIGCHGHW(sig, msr, DCD); 583 } else { 584 SIGCHGSW(sig, msr, DSR); 585 SIGCHGSW(sig, msr, CTS); 586 SIGCHGSW(sig, msr, DCD); 587 } 588 SIGCHGSW(sig, msr, RI); 589 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 590 return (sig); 591} 592 593int 594ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 595{ 596 struct uart_bas *bas; 597 int baudrate, divisor, error; 598 uint8_t efr, lcr; 599 600 bas = &sc->sc_bas; 601 error = 0; 602 uart_lock(sc->sc_hwmtx); 603 switch (request) { 604 case UART_IOCTL_BREAK: 605 lcr = uart_getreg(bas, REG_LCR); 606 if (data) 607 lcr |= LCR_SBREAK; 608 else 609 lcr &= ~LCR_SBREAK; 610 uart_setreg(bas, REG_LCR, lcr); 611 uart_barrier(bas); 612 break; 613 case UART_IOCTL_IFLOW: 614 lcr = uart_getreg(bas, REG_LCR); 615 uart_barrier(bas); 616 uart_setreg(bas, REG_LCR, 0xbf); 617 uart_barrier(bas); 618 efr = uart_getreg(bas, REG_EFR); 619 if (data) 620 efr |= EFR_RTS; 621 else 622 efr &= ~EFR_RTS; 623 uart_setreg(bas, REG_EFR, efr); 624 uart_barrier(bas); 625 uart_setreg(bas, REG_LCR, lcr); 626 uart_barrier(bas); 627 break; 628 case UART_IOCTL_OFLOW: 629 lcr = uart_getreg(bas, REG_LCR); 630 uart_barrier(bas); 631 uart_setreg(bas, REG_LCR, 0xbf); 632 uart_barrier(bas); 633 efr = uart_getreg(bas, REG_EFR); 634 if (data) 635 efr |= EFR_CTS; 636 else 637 efr &= ~EFR_CTS; 638 uart_setreg(bas, REG_EFR, efr); 639 uart_barrier(bas); 640 uart_setreg(bas, REG_LCR, lcr); 641 uart_barrier(bas); 642 break; 643 case UART_IOCTL_BAUD: 644 lcr = uart_getreg(bas, REG_LCR); 645 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 646 uart_barrier(bas); 647 divisor = uart_getreg(bas, REG_DLL) | 648 (uart_getreg(bas, REG_DLH) << 8); 649 uart_barrier(bas); 650 uart_setreg(bas, REG_LCR, lcr); 651 uart_barrier(bas); 652 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 653 if (baudrate > 0) 654 *(int*)data = baudrate; 655 else 656 error = ENXIO; 657 break; 658 default: 659 error = EINVAL; 660 break; 661 } 662 uart_unlock(sc->sc_hwmtx); 663 return (error); 664} 665 666int 667ns8250_bus_ipend(struct uart_softc *sc) 668{ 669 struct uart_bas *bas; 670 struct ns8250_softc *ns8250; 671 int ipend; 672 uint8_t iir, lsr; 673 674 ns8250 = (struct ns8250_softc *)sc; 675 bas = &sc->sc_bas; 676 uart_lock(sc->sc_hwmtx); 677 iir = uart_getreg(bas, REG_IIR); 678 679 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 680 (void)uart_getreg(bas, DW_REG_USR); 681 uart_unlock(sc->sc_hwmtx); 682 return (0); 683 } 684 if (iir & IIR_NOPEND) { 685 uart_unlock(sc->sc_hwmtx); 686 return (0); 687 } 688 ipend = 0; 689 if (iir & IIR_RXRDY) { 690 lsr = uart_getreg(bas, REG_LSR); 691 if (lsr & LSR_OE) 692 ipend |= SER_INT_OVERRUN; 693 if (lsr & LSR_BI) 694 ipend |= SER_INT_BREAK; 695 if (lsr & LSR_RXRDY) 696 ipend |= SER_INT_RXREADY; 697 } else { 698 if (iir & IIR_TXRDY) { 699 ipend |= SER_INT_TXIDLE; 700 uart_setreg(bas, REG_IER, ns8250->ier); 701 uart_barrier(bas); 702 } else 703 ipend |= SER_INT_SIGCHG; 704 } 705 if (ipend == 0) 706 ns8250_clrint(bas); 707 uart_unlock(sc->sc_hwmtx); 708 return (ipend); 709} 710 711int 712ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 713 int stopbits, int parity) 714{ 715 struct ns8250_softc *ns8250; 716 struct uart_bas *bas; 717 int error, limit; 718 719 ns8250 = (struct ns8250_softc*)sc; 720 bas = &sc->sc_bas; 721 uart_lock(sc->sc_hwmtx); 722 /* 723 * When using DW UART with BUSY detection it is necessary to wait 724 * until all serial transfers are finished before manipulating the 725 * line control. LCR will not be affected when UART is busy. 726 */ 727 if (ns8250->busy_detect != 0) { 728 /* 729 * Pick an arbitrary high limit to avoid getting stuck in 730 * an infinite loop in case when the hardware is broken. 731 */ 732 limit = 10 * 1024; 733 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 734 --limit) 735 DELAY(4); 736 737 if (limit <= 0) { 738 /* UART appears to be stuck */ 739 uart_unlock(sc->sc_hwmtx); 740 return (EIO); 741 } 742 } 743 744 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 745 uart_unlock(sc->sc_hwmtx); 746 return (error); 747} 748 749int 750ns8250_bus_probe(struct uart_softc *sc) 751{ 752 struct ns8250_softc *ns8250; 753 struct uart_bas *bas; 754 int count, delay, error, limit; 755 uint8_t lsr, mcr, ier; 756 757 ns8250 = (struct ns8250_softc *)sc; 758 bas = &sc->sc_bas; 759 760 error = ns8250_probe(bas); 761 if (error) 762 return (error); 763 764 mcr = MCR_IE; 765 if (sc->sc_sysdev == NULL) { 766 /* By using ns8250_init() we also set DTR and RTS. */ 767 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 768 } else 769 mcr |= MCR_DTR | MCR_RTS; 770 771 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 772 if (error) 773 return (error); 774 775 /* 776 * Set loopback mode. This avoids having garbage on the wire and 777 * also allows us send and receive data. We set DTR and RTS to 778 * avoid the possibility that automatic flow-control prevents 779 * any data from being sent. 780 */ 781 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 782 uart_barrier(bas); 783 784 /* 785 * Enable FIFOs. And check that the UART has them. If not, we're 786 * done. Since this is the first time we enable the FIFOs, we reset 787 * them. 788 */ 789 uart_setreg(bas, REG_FCR, FCR_ENABLE); 790 uart_barrier(bas); 791 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 792 /* 793 * NS16450 or INS8250. We don't bother to differentiate 794 * between them. They're too old to be interesting. 795 */ 796 uart_setreg(bas, REG_MCR, mcr); 797 uart_barrier(bas); 798 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 799 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 800 return (0); 801 } 802 803 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 804 uart_barrier(bas); 805 806 count = 0; 807 delay = ns8250_delay(bas); 808 809 /* We have FIFOs. Drain the transmitter and receiver. */ 810 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 811 if (error) { 812 uart_setreg(bas, REG_MCR, mcr); 813 uart_setreg(bas, REG_FCR, 0); 814 uart_barrier(bas); 815 goto describe; 816 } 817 818 /* 819 * We should have a sufficiently clean "pipe" to determine the 820 * size of the FIFOs. We send as much characters as is reasonable 821 * and wait for the overflow bit in the LSR register to be 822 * asserted, counting the characters as we send them. Based on 823 * that count we know the FIFO size. 824 */ 825 do { 826 uart_setreg(bas, REG_DATA, 0); 827 uart_barrier(bas); 828 count++; 829 830 limit = 30; 831 lsr = 0; 832 /* 833 * LSR bits are cleared upon read, so we must accumulate 834 * them to be able to test LSR_OE below. 835 */ 836 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 837 --limit) 838 DELAY(delay); 839 if (limit == 0) { 840 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 841 uart_setreg(bas, REG_IER, ier); 842 uart_setreg(bas, REG_MCR, mcr); 843 uart_setreg(bas, REG_FCR, 0); 844 uart_barrier(bas); 845 count = 0; 846 goto describe; 847 } 848 } while ((lsr & LSR_OE) == 0 && count < 130); 849 count--; 850 851 uart_setreg(bas, REG_MCR, mcr); 852 853 /* Reset FIFOs. */ 854 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 855 856 describe: 857 if (count >= 14 && count <= 16) { 858 sc->sc_rxfifosz = 16; 859 device_set_desc(sc->sc_dev, "16550 or compatible"); 860 } else if (count >= 28 && count <= 32) { 861 sc->sc_rxfifosz = 32; 862 device_set_desc(sc->sc_dev, "16650 or compatible"); 863 } else if (count >= 56 && count <= 64) { 864 sc->sc_rxfifosz = 64; 865 device_set_desc(sc->sc_dev, "16750 or compatible"); 866 } else if (count >= 112 && count <= 128) { 867 sc->sc_rxfifosz = 128; 868 device_set_desc(sc->sc_dev, "16950 or compatible"); 869 } else { 870 sc->sc_rxfifosz = 16; 871 device_set_desc(sc->sc_dev, 872 "Non-standard ns8250 class UART with FIFOs"); 873 } 874 875 /* 876 * Force the Tx FIFO size to 16 bytes for now. We don't program the 877 * Tx trigger. Also, we assume that all data has been sent when the 878 * interrupt happens. 879 */ 880 sc->sc_txfifosz = 16; 881 882#if 0 883 /* 884 * XXX there are some issues related to hardware flow control and 885 * it's likely that uart(4) is the cause. This basically needs more 886 * investigation, but we avoid using for hardware flow control 887 * until then. 888 */ 889 /* 16650s or higher have automatic flow control. */ 890 if (sc->sc_rxfifosz > 16) { 891 sc->sc_hwiflow = 1; 892 sc->sc_hwoflow = 1; 893 } 894#endif 895 896 return (0); 897} 898 899int 900ns8250_bus_receive(struct uart_softc *sc) 901{ 902 struct uart_bas *bas; 903 int xc; 904 uint8_t lsr; 905 906 bas = &sc->sc_bas; 907 uart_lock(sc->sc_hwmtx); 908 lsr = uart_getreg(bas, REG_LSR); 909 while (lsr & LSR_RXRDY) { 910 if (uart_rx_full(sc)) { 911 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 912 break; 913 } 914 xc = uart_getreg(bas, REG_DATA); 915 if (lsr & LSR_FE) 916 xc |= UART_STAT_FRAMERR; 917 if (lsr & LSR_PE) 918 xc |= UART_STAT_PARERR; 919 uart_rx_put(sc, xc); 920 lsr = uart_getreg(bas, REG_LSR); 921 } 922 /* Discard everything left in the Rx FIFO. */ 923 while (lsr & LSR_RXRDY) { 924 (void)uart_getreg(bas, REG_DATA); 925 uart_barrier(bas); 926 lsr = uart_getreg(bas, REG_LSR); 927 } 928 uart_unlock(sc->sc_hwmtx); 929 return (0); 930} 931 932int 933ns8250_bus_setsig(struct uart_softc *sc, int sig) 934{ 935 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 936 struct uart_bas *bas; 937 uint32_t new, old; 938 939 bas = &sc->sc_bas; 940 do { 941 old = sc->sc_hwsig; 942 new = old; 943 if (sig & SER_DDTR) { 944 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 945 } 946 if (sig & SER_DRTS) { 947 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 948 } 949 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 950 uart_lock(sc->sc_hwmtx); 951 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 952 if (new & SER_DTR) 953 ns8250->mcr |= MCR_DTR; 954 if (new & SER_RTS) 955 ns8250->mcr |= MCR_RTS; 956 uart_setreg(bas, REG_MCR, ns8250->mcr); 957 uart_barrier(bas); 958 uart_unlock(sc->sc_hwmtx); 959 return (0); 960} 961 962int 963ns8250_bus_transmit(struct uart_softc *sc) 964{ 965 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 966 struct uart_bas *bas; 967 int i; 968 969 bas = &sc->sc_bas; 970 uart_lock(sc->sc_hwmtx); 971 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 972 ; 973 for (i = 0; i < sc->sc_txdatasz; i++) { 974 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 975 uart_barrier(bas); 976 } 977 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 978 uart_barrier(bas); 979 if (broken_txfifo) 980 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 981 else 982 sc->sc_txbusy = 1; 983 uart_unlock(sc->sc_hwmtx); 984 if (broken_txfifo) 985 uart_sched_softih(sc, SER_INT_TXIDLE); 986 return (0); 987} 988 989void 990ns8250_bus_grab(struct uart_softc *sc) 991{ 992 struct uart_bas *bas = &sc->sc_bas; 993 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 994 u_char ier; 995 996 /* 997 * turn off all interrupts to enter polling mode. Leave the 998 * saved mask alone. We'll restore whatever it was in ungrab. 999 * All pending interrupt signals are reset when IER is set to 0. 1000 */ 1001 uart_lock(sc->sc_hwmtx); 1002 ier = uart_getreg(bas, REG_IER); 1003 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1004 uart_barrier(bas); 1005 uart_unlock(sc->sc_hwmtx); 1006} 1007 1008void 1009ns8250_bus_ungrab(struct uart_softc *sc) 1010{ 1011 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1012 struct uart_bas *bas = &sc->sc_bas; 1013 1014 /* 1015 * Restore previous interrupt mask 1016 */ 1017 uart_lock(sc->sc_hwmtx); 1018 uart_setreg(bas, REG_IER, ns8250->ier); 1019 uart_barrier(bas); 1020 uart_unlock(sc->sc_hwmtx); 1021} 1022