1/*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: releng/11.0/sys/dev/uart/uart_dev_z8530.c 281438 2015-04-11 17:16:23Z andrew $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/conf.h> 34#include <machine/bus.h> 35 36#include <dev/uart/uart.h> 37#include <dev/uart/uart_cpu.h> 38#include <dev/uart/uart_bus.h> 39 40#include <dev/ic/z8530.h> 41 42#include "uart_if.h" 43 44#define DEFAULT_RCLK 307200 45 46/* Hack! */ 47#ifdef __powerpc__ 48#define UART_PCLK 0 49#else 50#define UART_PCLK MCB2_PCLK 51#endif 52 53/* Multiplexed I/O. */ 54static __inline void 55uart_setmreg(struct uart_bas *bas, int reg, int val) 56{ 57 58 uart_setreg(bas, REG_CTRL, reg); 59 uart_barrier(bas); 60 uart_setreg(bas, REG_CTRL, val); 61} 62 63static __inline uint8_t 64uart_getmreg(struct uart_bas *bas, int reg) 65{ 66 67 uart_setreg(bas, REG_CTRL, reg); 68 uart_barrier(bas); 69 return (uart_getreg(bas, REG_CTRL)); 70} 71 72static int 73z8530_divisor(int rclk, int baudrate) 74{ 75 int act_baud, divisor, error; 76 77 if (baudrate == 0) 78 return (-1); 79 80 divisor = (rclk + baudrate) / (baudrate << 1) - 2; 81 if (divisor < 0 || divisor >= 65536) 82 return (-1); 83 act_baud = rclk / 2 / (divisor + 2); 84 85 /* 10 times error in percent: */ 86 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1; 87 88 /* 3.0% maximum error tolerance: */ 89 if (error < -30 || error > 30) 90 return (-1); 91 92 return (divisor); 93} 94 95static int 96z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 97 int parity, uint8_t *tpcp) 98{ 99 int divisor; 100 uint8_t mpm, rpc, tpc; 101 102 rpc = RPC_RXE; 103 mpm = MPM_CM16; 104 tpc = TPC_TXE | (*tpcp & (TPC_DTR | TPC_RTS)); 105 106 if (databits >= 8) { 107 rpc |= RPC_RB8; 108 tpc |= TPC_TB8; 109 } else if (databits == 7) { 110 rpc |= RPC_RB7; 111 tpc |= TPC_TB7; 112 } else if (databits == 6) { 113 rpc |= RPC_RB6; 114 tpc |= TPC_TB6; 115 } else { 116 rpc |= RPC_RB5; 117 tpc |= TPC_TB5; 118 } 119 mpm |= (stopbits > 1) ? MPM_SB2 : MPM_SB1; 120 switch (parity) { 121 case UART_PARITY_EVEN: mpm |= MPM_PE | MPM_EVEN; break; 122 case UART_PARITY_NONE: break; 123 case UART_PARITY_ODD: mpm |= MPM_PE; break; 124 default: return (EINVAL); 125 } 126 127 if (baudrate > 0) { 128 divisor = z8530_divisor(bas->rclk, baudrate); 129 if (divisor == -1) 130 return (EINVAL); 131 } else 132 divisor = -1; 133 134 uart_setmreg(bas, WR_MCB2, UART_PCLK); 135 uart_barrier(bas); 136 137 if (divisor >= 0) { 138 uart_setmreg(bas, WR_TCL, divisor & 0xff); 139 uart_barrier(bas); 140 uart_setmreg(bas, WR_TCH, (divisor >> 8) & 0xff); 141 uart_barrier(bas); 142 } 143 144 uart_setmreg(bas, WR_RPC, rpc); 145 uart_barrier(bas); 146 uart_setmreg(bas, WR_MPM, mpm); 147 uart_barrier(bas); 148 uart_setmreg(bas, WR_TPC, tpc); 149 uart_barrier(bas); 150 uart_setmreg(bas, WR_MCB2, UART_PCLK | MCB2_BRGE); 151 uart_barrier(bas); 152 *tpcp = tpc; 153 return (0); 154} 155 156static int 157z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits, 158 int parity) 159{ 160 uint8_t tpc; 161 162 if (bas->rclk == 0) 163 bas->rclk = DEFAULT_RCLK; 164 165 /* Assume we don't need to perform a full hardware reset. */ 166 switch (bas->chan) { 167 case 1: 168 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRA); 169 break; 170 case 2: 171 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRB); 172 break; 173 } 174 uart_barrier(bas); 175 /* Set clock sources. */ 176 uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG); 177 uart_setmreg(bas, WR_MCB2, UART_PCLK); 178 uart_barrier(bas); 179 /* Set data encoding. */ 180 uart_setmreg(bas, WR_MCB1, MCB1_NRZ); 181 uart_barrier(bas); 182 183 tpc = TPC_DTR | TPC_RTS; 184 z8530_param(bas, baudrate, databits, stopbits, parity, &tpc); 185 return (int)tpc; 186} 187 188/* 189 * Low-level UART interface. 190 */ 191static int z8530_probe(struct uart_bas *bas); 192static void z8530_init(struct uart_bas *bas, int, int, int, int); 193static void z8530_term(struct uart_bas *bas); 194static void z8530_putc(struct uart_bas *bas, int); 195static int z8530_rxready(struct uart_bas *bas); 196static int z8530_getc(struct uart_bas *bas, struct mtx *); 197 198static struct uart_ops uart_z8530_ops = { 199 .probe = z8530_probe, 200 .init = z8530_init, 201 .term = z8530_term, 202 .putc = z8530_putc, 203 .rxready = z8530_rxready, 204 .getc = z8530_getc, 205}; 206 207static int 208z8530_probe(struct uart_bas *bas) 209{ 210 211 return (0); 212} 213 214static void 215z8530_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 216 int parity) 217{ 218 219 z8530_setup(bas, baudrate, databits, stopbits, parity); 220} 221 222static void 223z8530_term(struct uart_bas *bas) 224{ 225} 226 227static void 228z8530_putc(struct uart_bas *bas, int c) 229{ 230 231 while (!(uart_getreg(bas, REG_CTRL) & BES_TXE)) 232 ; 233 uart_setreg(bas, REG_DATA, c); 234 uart_barrier(bas); 235} 236 237static int 238z8530_rxready(struct uart_bas *bas) 239{ 240 241 return ((uart_getreg(bas, REG_CTRL) & BES_RXA) != 0 ? 1 : 0); 242} 243 244static int 245z8530_getc(struct uart_bas *bas, struct mtx *hwmtx) 246{ 247 int c; 248 249 uart_lock(hwmtx); 250 251 while (!(uart_getreg(bas, REG_CTRL) & BES_RXA)) { 252 uart_unlock(hwmtx); 253 DELAY(10); 254 uart_lock(hwmtx); 255 } 256 257 c = uart_getreg(bas, REG_DATA); 258 259 uart_unlock(hwmtx); 260 261 return (c); 262} 263 264/* 265 * High-level UART interface. 266 */ 267struct z8530_softc { 268 struct uart_softc base; 269 uint8_t tpc; 270 uint8_t txidle; 271}; 272 273static int z8530_bus_attach(struct uart_softc *); 274static int z8530_bus_detach(struct uart_softc *); 275static int z8530_bus_flush(struct uart_softc *, int); 276static int z8530_bus_getsig(struct uart_softc *); 277static int z8530_bus_ioctl(struct uart_softc *, int, intptr_t); 278static int z8530_bus_ipend(struct uart_softc *); 279static int z8530_bus_param(struct uart_softc *, int, int, int, int); 280static int z8530_bus_probe(struct uart_softc *); 281static int z8530_bus_receive(struct uart_softc *); 282static int z8530_bus_setsig(struct uart_softc *, int); 283static int z8530_bus_transmit(struct uart_softc *); 284static void z8530_bus_grab(struct uart_softc *); 285static void z8530_bus_ungrab(struct uart_softc *); 286 287static kobj_method_t z8530_methods[] = { 288 KOBJMETHOD(uart_attach, z8530_bus_attach), 289 KOBJMETHOD(uart_detach, z8530_bus_detach), 290 KOBJMETHOD(uart_flush, z8530_bus_flush), 291 KOBJMETHOD(uart_getsig, z8530_bus_getsig), 292 KOBJMETHOD(uart_ioctl, z8530_bus_ioctl), 293 KOBJMETHOD(uart_ipend, z8530_bus_ipend), 294 KOBJMETHOD(uart_param, z8530_bus_param), 295 KOBJMETHOD(uart_probe, z8530_bus_probe), 296 KOBJMETHOD(uart_receive, z8530_bus_receive), 297 KOBJMETHOD(uart_setsig, z8530_bus_setsig), 298 KOBJMETHOD(uart_transmit, z8530_bus_transmit), 299 KOBJMETHOD(uart_grab, z8530_bus_grab), 300 KOBJMETHOD(uart_ungrab, z8530_bus_ungrab), 301 { 0, 0 } 302}; 303 304struct uart_class uart_z8530_class = { 305 "z8530", 306 z8530_methods, 307 sizeof(struct z8530_softc), 308 .uc_ops = &uart_z8530_ops, 309 .uc_range = 2, 310 .uc_rclk = DEFAULT_RCLK, 311 .uc_rshift = 0 312}; 313 314#define SIGCHG(c, i, s, d) \ 315 if (c) { \ 316 i |= (i & s) ? s : s | d; \ 317 } else { \ 318 i = (i & s) ? (i & ~s) | d : i; \ 319 } 320 321static int 322z8530_bus_attach(struct uart_softc *sc) 323{ 324 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 325 struct uart_bas *bas; 326 struct uart_devinfo *di; 327 328 bas = &sc->sc_bas; 329 if (sc->sc_sysdev != NULL) { 330 di = sc->sc_sysdev; 331 z8530->tpc = TPC_DTR|TPC_RTS; 332 z8530_param(bas, di->baudrate, di->databits, di->stopbits, 333 di->parity, &z8530->tpc); 334 } else { 335 z8530->tpc = z8530_setup(bas, 9600, 8, 1, UART_PARITY_NONE); 336 z8530->tpc &= ~(TPC_DTR|TPC_RTS); 337 } 338 z8530->txidle = 1; /* Report SER_INT_TXIDLE. */ 339 340 (void)z8530_bus_getsig(sc); 341 342 uart_setmreg(bas, WR_IC, IC_BRK | IC_CTS | IC_DCD); 343 uart_barrier(bas); 344 uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE | IDT_RIA); 345 uart_barrier(bas); 346 uart_setmreg(bas, WR_IV, 0); 347 uart_barrier(bas); 348 uart_setmreg(bas, WR_TPC, z8530->tpc); 349 uart_barrier(bas); 350 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_MIE); 351 uart_barrier(bas); 352 return (0); 353} 354 355static int 356z8530_bus_detach(struct uart_softc *sc) 357{ 358 359 return (0); 360} 361 362static int 363z8530_bus_flush(struct uart_softc *sc, int what) 364{ 365 366 return (0); 367} 368 369static int 370z8530_bus_getsig(struct uart_softc *sc) 371{ 372 uint32_t new, old, sig; 373 uint8_t bes; 374 375 do { 376 old = sc->sc_hwsig; 377 sig = old; 378 uart_lock(sc->sc_hwmtx); 379 bes = uart_getmreg(&sc->sc_bas, RR_BES); 380 uart_unlock(sc->sc_hwmtx); 381 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS); 382 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD); 383 SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR); 384 new = sig & ~SER_MASK_DELTA; 385 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 386 return (sig); 387} 388 389static int 390z8530_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 391{ 392 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 393 struct uart_bas *bas; 394 int baudrate, divisor, error; 395 396 bas = &sc->sc_bas; 397 error = 0; 398 uart_lock(sc->sc_hwmtx); 399 switch (request) { 400 case UART_IOCTL_BREAK: 401 if (data) 402 z8530->tpc |= TPC_BRK; 403 else 404 z8530->tpc &= ~TPC_BRK; 405 uart_setmreg(bas, WR_TPC, z8530->tpc); 406 uart_barrier(bas); 407 break; 408 case UART_IOCTL_BAUD: 409 divisor = uart_getmreg(bas, RR_TCH); 410 divisor = (divisor << 8) | uart_getmreg(bas, RR_TCL); 411 baudrate = bas->rclk / 2 / (divisor + 2); 412 *(int*)data = baudrate; 413 break; 414 default: 415 error = EINVAL; 416 break; 417 } 418 uart_unlock(sc->sc_hwmtx); 419 return (error); 420} 421 422static int 423z8530_bus_ipend(struct uart_softc *sc) 424{ 425 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 426 struct uart_bas *bas; 427 int ipend; 428 uint32_t sig; 429 uint8_t bes, ip, iv, src; 430 431 bas = &sc->sc_bas; 432 ipend = 0; 433 434 uart_lock(sc->sc_hwmtx); 435 switch (bas->chan) { 436 case 1: 437 ip = uart_getmreg(bas, RR_IP); 438 break; 439 case 2: /* XXX hack!!! */ 440 iv = uart_getmreg(bas, RR_IV) & 0x0E; 441 switch (iv) { 442 case IV_TEB: ip = IP_TIA; break; 443 case IV_XSB: ip = IP_SIA; break; 444 case IV_RAB: ip = IP_RIA; break; 445 default: ip = 0; break; 446 } 447 break; 448 default: 449 ip = 0; 450 break; 451 } 452 453 if (ip & IP_RIA) 454 ipend |= SER_INT_RXREADY; 455 456 if (ip & IP_TIA) { 457 uart_setreg(bas, REG_CTRL, CR_RSTTXI); 458 uart_barrier(bas); 459 if (z8530->txidle) { 460 ipend |= SER_INT_TXIDLE; 461 z8530->txidle = 0; /* Mask SER_INT_TXIDLE. */ 462 } 463 } 464 465 if (ip & IP_SIA) { 466 uart_setreg(bas, REG_CTRL, CR_RSTXSI); 467 uart_barrier(bas); 468 bes = uart_getmreg(bas, RR_BES); 469 if (bes & BES_BRK) 470 ipend |= SER_INT_BREAK; 471 sig = sc->sc_hwsig; 472 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS); 473 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD); 474 SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR); 475 if (sig & SER_MASK_DELTA) 476 ipend |= SER_INT_SIGCHG; 477 src = uart_getmreg(bas, RR_SRC); 478 if (src & SRC_OVR) { 479 uart_setreg(bas, REG_CTRL, CR_RSTERR); 480 uart_barrier(bas); 481 ipend |= SER_INT_OVERRUN; 482 } 483 } 484 485 if (ipend) { 486 uart_setreg(bas, REG_CTRL, CR_RSTIUS); 487 uart_barrier(bas); 488 } 489 490 uart_unlock(sc->sc_hwmtx); 491 492 return (ipend); 493} 494 495static int 496z8530_bus_param(struct uart_softc *sc, int baudrate, int databits, 497 int stopbits, int parity) 498{ 499 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 500 int error; 501 502 uart_lock(sc->sc_hwmtx); 503 error = z8530_param(&sc->sc_bas, baudrate, databits, stopbits, parity, 504 &z8530->tpc); 505 uart_unlock(sc->sc_hwmtx); 506 return (error); 507} 508 509static int 510z8530_bus_probe(struct uart_softc *sc) 511{ 512 char buf[80]; 513 int error; 514 char ch; 515 516 error = z8530_probe(&sc->sc_bas); 517 if (error) 518 return (error); 519 520 sc->sc_rxfifosz = 3; 521 sc->sc_txfifosz = 1; 522 523 ch = sc->sc_bas.chan - 1 + 'A'; 524 525 snprintf(buf, sizeof(buf), "z8530, channel %c", ch); 526 device_set_desc_copy(sc->sc_dev, buf); 527 return (0); 528} 529 530static int 531z8530_bus_receive(struct uart_softc *sc) 532{ 533 struct uart_bas *bas; 534 int xc; 535 uint8_t bes, src; 536 537 bas = &sc->sc_bas; 538 uart_lock(sc->sc_hwmtx); 539 bes = uart_getmreg(bas, RR_BES); 540 while (bes & BES_RXA) { 541 if (uart_rx_full(sc)) { 542 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 543 break; 544 } 545 xc = uart_getreg(bas, REG_DATA); 546 uart_barrier(bas); 547 src = uart_getmreg(bas, RR_SRC); 548 if (src & SRC_FE) 549 xc |= UART_STAT_FRAMERR; 550 if (src & SRC_PE) 551 xc |= UART_STAT_PARERR; 552 if (src & SRC_OVR) 553 xc |= UART_STAT_OVERRUN; 554 uart_rx_put(sc, xc); 555 if (src & (SRC_FE | SRC_PE | SRC_OVR)) { 556 uart_setreg(bas, REG_CTRL, CR_RSTERR); 557 uart_barrier(bas); 558 } 559 bes = uart_getmreg(bas, RR_BES); 560 } 561 /* Discard everything left in the Rx FIFO. */ 562 while (bes & BES_RXA) { 563 (void)uart_getreg(bas, REG_DATA); 564 uart_barrier(bas); 565 src = uart_getmreg(bas, RR_SRC); 566 if (src & (SRC_FE | SRC_PE | SRC_OVR)) { 567 uart_setreg(bas, REG_CTRL, CR_RSTERR); 568 uart_barrier(bas); 569 } 570 bes = uart_getmreg(bas, RR_BES); 571 } 572 uart_unlock(sc->sc_hwmtx); 573 return (0); 574} 575 576static int 577z8530_bus_setsig(struct uart_softc *sc, int sig) 578{ 579 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 580 struct uart_bas *bas; 581 uint32_t new, old; 582 583 bas = &sc->sc_bas; 584 do { 585 old = sc->sc_hwsig; 586 new = old; 587 if (sig & SER_DDTR) { 588 SIGCHG(sig & SER_DTR, new, SER_DTR, 589 SER_DDTR); 590 } 591 if (sig & SER_DRTS) { 592 SIGCHG(sig & SER_RTS, new, SER_RTS, 593 SER_DRTS); 594 } 595 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 596 597 uart_lock(sc->sc_hwmtx); 598 if (new & SER_DTR) 599 z8530->tpc |= TPC_DTR; 600 else 601 z8530->tpc &= ~TPC_DTR; 602 if (new & SER_RTS) 603 z8530->tpc |= TPC_RTS; 604 else 605 z8530->tpc &= ~TPC_RTS; 606 uart_setmreg(bas, WR_TPC, z8530->tpc); 607 uart_barrier(bas); 608 uart_unlock(sc->sc_hwmtx); 609 return (0); 610} 611 612static int 613z8530_bus_transmit(struct uart_softc *sc) 614{ 615 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 616 struct uart_bas *bas; 617 618 bas = &sc->sc_bas; 619 uart_lock(sc->sc_hwmtx); 620 while (!(uart_getmreg(bas, RR_BES) & BES_TXE)) 621 ; 622 uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]); 623 uart_barrier(bas); 624 sc->sc_txbusy = 1; 625 z8530->txidle = 1; /* Report SER_INT_TXIDLE again. */ 626 uart_unlock(sc->sc_hwmtx); 627 return (0); 628} 629 630static void 631z8530_bus_grab(struct uart_softc *sc) 632{ 633 struct uart_bas *bas; 634 635 bas = &sc->sc_bas; 636 uart_lock(sc->sc_hwmtx); 637 uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE); 638 uart_barrier(bas); 639 uart_unlock(sc->sc_hwmtx); 640} 641 642static void 643z8530_bus_ungrab(struct uart_softc *sc) 644{ 645 struct uart_bas *bas; 646 647 bas = &sc->sc_bas; 648 uart_lock(sc->sc_hwmtx); 649 uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE | IDT_RIA); 650 uart_barrier(bas); 651 uart_unlock(sc->sc_hwmtx); 652} 653