/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | RegisterBank.h | 92 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) { argument
|
H A D | RegisterBankInfo.h | 60 const RegisterBank *RegBank; member in struct:llvm::RegisterBankInfo::PartialMapping 65 PartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) argument
|
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | CodeGenTarget.h | 53 mutable std::unique_ptr<CodeGenRegBank> RegBank; member in class:llvm::CodeGenTarget
|
H A D | CodeGenTarget.cpp | 301 getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy, CodeGenRegBank &RegBank, const CodeGenSubRegIndex *SubIdx) const argument
|
H A D | RegisterInfoEmitter.cpp | 62 CodeGenRegBank &RegBank = Target.getRegBank(); local 194 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, argument 692 emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank, const std::string &ClName) argument 762 emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank, const std::string &ClName) argument 863 runMCDesc(raw_ostream &OS, CodeGenTarget &Target, CodeGenRegBank &RegBank) argument 1130 runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, CodeGenRegBank &RegBank) argument 1200 runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, CodeGenRegBank &RegBank) argument 1605 CodeGenRegBank &RegBank = Target.getRegBank(); local 1616 CodeGenRegBank &RegBank = Target.getRegBank(); local [all...] |
H A D | CodeGenRegisters.cpp | 76 void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) { argument 168 void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) { argument 255 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) { argument 267 CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) { argument 465 computeSecondarySubRegs(CodeGenRegBank &RegBank) argument 546 computeSuperRegs(CodeGenRegBank &RegBank) argument 741 CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R) argument 817 CodeGenRegisterClass(CodeGenRegBank &RegBank, StringRef Name, Key Props) argument 836 inheritProperties(CodeGenRegBank &RegBank) argument 940 computeSubClasses(CodeGenRegBank &RegBank) argument 991 getMatchingSubClassWithSubRegs( CodeGenRegBank &RegBank, const CodeGenSubRegIndex *SubIdx) const argument 1078 buildRegUnitSet(const CodeGenRegBank &RegBank, std::vector<unsigned> &RegUnits) const argument 1583 computeUberSets(std::vector<UberRegSet> &UberSets, std::vector<UberRegSet*> &RegSets, CodeGenRegBank &RegBank) argument 1644 computeUberWeights(std::vector<UberRegSet> &UberSets, CodeGenRegBank &RegBank) argument 1701 normalizeWeight(CodeGenRegister *Reg, std::vector<UberRegSet> &UberSets, std::vector<UberRegSet*> &RegSets, BitVector &NormalRegs, CodeGenRegister::RegUnitList &NormalUnits, CodeGenRegBank &RegBank) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/MIRParser/ |
H A D | MIParser.h | 41 const RegisterBank *RegBank; member in union:llvm::VRegInfo::__anon1458
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/ |
H A D | MIRParser.cpp | 529 const RegisterBank *RegBank = Target->getRegBank(VReg.Class.Value); local
|
H A D | MIParser.cpp | 298 const auto &RegBank = RBI->getRegBank(I); local 1305 const RegisterBank *RegBank = nullptr; local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MachineRegisterInfo.cpp | 63 setRegBank(unsigned Reg, const RegisterBank &RegBank) argument
|
H A D | MachineVerifier.cpp | 1727 const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg); local
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | RegisterBankInfo.cpp | 72 const RegisterBank &RegBank = getRegBank(Idx); local 125 const RegisterBank &RegBank = getRegBankFromRegClass(*RC, MRI.getType(Reg)); local 267 hashPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank *RegBank) argument 531 OS << *RegBank; local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMInstructionSelector.cpp | 191 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); local 1089 unsigned RegBank local 357 selectLoadStoreOpCode(unsigned Opc, unsigned RegBank, unsigned Size) const argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstructionSelector.cpp | 199 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); local 1368 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); local 1437 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); local
|