/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/ |
H A D | Thumb1FrameLowering.cpp | 84 unsigned Reg = CSI[i].getReg(); local 177 static bool isCalleeSavedRegister(unsigned Reg, const uint16_t *CSRegs) { argument 307 unsigned Reg = CSI[i-1].getReg(); local 348 unsigned Reg = CSI[i-1].getReg(); local [all...] |
H A D | Thumb2ITBlockPass.cpp | 65 unsigned Reg = MO.getReg(); local 75 unsigned Reg = LocalUses[i]; local 82 unsigned Reg local [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Hexagon/ |
H A D | HexagonFrameLowering.cpp | 213 unsigned uniqueSuperReg(unsigned Reg, const TargetRegisterInfo *TRI) { argument 243 unsigned Reg = CSI[i].getReg(); local 298 unsigned Reg = CSI[i].getReg(); local [all...] |
H A D | HexagonNewValueJump.cpp | 137 unsigned Reg = II->getOperand(i).getReg(); local
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MBlaze/ |
H A D | MBlazeAsmPrinter.cpp | 136 unsigned Reg = CSI[i].getReg(); local
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H A D | MBlazeMachineFunction.h | 158 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument 161 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 42 SDValue Reg; member in struct:__anon10220::MSP430ISelAddressMode::__anon10222 [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCCodeEmitter.cpp | 180 unsigned Reg = MO.getReg(); local
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Mips/ |
H A D | MipsSEInstrInfo.cpp | 264 unsigned Reg = loadImmediate(Amount, MBB, I, DL, 0); local
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ |
H A D | TargetRegisterInfo.cpp | 42 OS << "%physreg" << Reg; local
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/X86/ |
H A D | X86CodeEmitter.cpp | 179 unsigned Reg = MO.getReg(); local
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H A D | X86InstrBuilder.h | 44 unsigned Reg; member in union:llvm::X86AddressMode::__anon10316 90 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { argument 107 addRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, bool isKill, int Offset) argument [all...] |
H A D | X86MCInstLower.cpp | 205 unsigned Reg = MI->getOperand(OpNo).getReg(); local 215 unsigned Reg = MI->getOperand(OpNo+i).getReg(); local 245 unsigned Reg = Inst.getOperand(0).getReg(); local 278 unsigned Reg = Inst.getOperand(RegOp).getReg(); local 660 unsigned Reg = MI->getOperand(0).getReg(); local [all...] |
H A D | X86MachineFunctionInfo.h | 118 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument 121 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/XCore/ |
H A D | XCoreFrameLowering.cpp | 204 unsigned Reg = CSI.getReg(); local 293 unsigned Reg = it->getReg(); local 319 unsigned Reg = it->getReg(); local
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H A D | XCoreRegisterInfo.cpp | 210 unsigned Reg = MI.getOperand(0).getReg(); local [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/utils/TableGen/ |
H A D | PseudoLoweringEmitter.cpp | 27 enum MapKind { Operand, Imm, Reg }; enumerator in enum:__anon10638::PseudoLoweringEmitter::OpData::MapKind 32 Record *Reg; // Physical register. member in union:__anon10638::PseudoLoweringEmitter::OpData::__anon10639 240 Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg; local [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/include/llvm/CodeGen/ |
H A D | CallingConvLower.h | 243 unsigned AllocateReg(unsigned Reg) { argument 250 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { argument 266 unsigned Reg = Regs[FirstUnalloc]; local 279 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; local [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/include/llvm/MC/ |
H A D | MCInst.h | 69 void setReg(unsigned Reg) { argument 111 static MCOperand CreateReg(unsigned Reg) { argument
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/macosx-10.10.1/llvmCore-3425.0.34/lib/CodeGen/ |
H A D | MachineInstr.cpp | 50 void MachineOperand::setReg(unsigned Reg) { argument 70 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, argument 80 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) { argument 130 ChangeToRegister(unsigned Reg, bool isDef, bool isImp, bool isKill, bool isDead, bool isUndef, bool isDebug) argument [all...] |
H A D | MachineSink.cpp | 157 MachineSinking::AllUsesDominatedByBlock(unsigned Reg, argument 314 unsigned Reg = MO.getReg(); local 433 isProfitableToSinkTo(unsigned Reg, MachineInstr *MI, MachineBasicBlock *MBB, MachineBasicBlock *SuccToSinkTo) argument 489 unsigned Reg = MO.getReg(); local 612 unsigned Reg = MO.getReg(); local [all...] |
H A D | PostRASchedulerList.cpp | 428 unsigned Reg = *I; local 441 unsigned Reg = *I; local 512 unsigned Reg = MO.getReg(); local 532 unsigned Reg = MO.getReg(); local 567 unsigned Reg = MO.getReg(); local [all...] |
H A D | PrologEpilogInserter.cpp | 229 unsigned Reg = CSRegs[i]; local 247 unsigned Reg = I->getReg(); local 315 unsigned Reg = CSI[i].getReg(); local 342 unsigned Reg = CSI[i].getReg(); local 390 unsigned Reg = blockCSI[i].getReg(); local 441 unsigned Reg = blockCSI[i].getReg(); local 832 unsigned Reg = MO.getReg(); local [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGFast.cpp | 380 void ScheduleDAGFast::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, argument 423 static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, argument 438 static bool CheckForLiveRegDef(SUnit *SU, unsigned Reg, argument 492 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); local 562 unsigned Reg = LRegs[0]; local [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/ExecutionEngine/JIT/ |
H A D | JITDwarfEmitter.cpp | 120 unsigned Reg = RI->getDwarfRegNum(Src.getReg(), true); local
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