Searched defs:Reg (Results 51 - 75 of 166) sorted by relevance

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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/
H A DThumb1FrameLowering.cpp84 unsigned Reg = CSI[i].getReg(); local
177 static bool isCalleeSavedRegister(unsigned Reg, const uint16_t *CSRegs) { argument
307 unsigned Reg = CSI[i-1].getReg(); local
348 unsigned Reg = CSI[i-1].getReg(); local
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H A DThumb2ITBlockPass.cpp65 unsigned Reg = MO.getReg(); local
75 unsigned Reg = LocalUses[i]; local
82 unsigned Reg local
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp213 unsigned uniqueSuperReg(unsigned Reg, const TargetRegisterInfo *TRI) { argument
243 unsigned Reg = CSI[i].getReg(); local
298 unsigned Reg = CSI[i].getReg(); local
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H A DHexagonNewValueJump.cpp137 unsigned Reg = II->getOperand(i).getReg(); local
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MBlaze/
H A DMBlazeAsmPrinter.cpp136 unsigned Reg = CSI[i].getReg(); local
H A DMBlazeMachineFunction.h158 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
161 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp42 SDValue Reg; member in struct:__anon10220::MSP430ISelAddressMode::__anon10222
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp180 unsigned Reg = MO.getReg(); local
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp264 unsigned Reg = loadImmediate(Amount, MBB, I, DL, 0); local
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/
H A DTargetRegisterInfo.cpp42 OS << "%physreg" << Reg; local
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/X86/
H A DX86CodeEmitter.cpp179 unsigned Reg = MO.getReg(); local
H A DX86InstrBuilder.h44 unsigned Reg; member in union:llvm::X86AddressMode::__anon10316
90 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { argument
107 addRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, bool isKill, int Offset) argument
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H A DX86MCInstLower.cpp205 unsigned Reg = MI->getOperand(OpNo).getReg(); local
215 unsigned Reg = MI->getOperand(OpNo+i).getReg(); local
245 unsigned Reg = Inst.getOperand(0).getReg(); local
278 unsigned Reg = Inst.getOperand(RegOp).getReg(); local
660 unsigned Reg = MI->getOperand(0).getReg(); local
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H A DX86MachineFunctionInfo.h118 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
121 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/XCore/
H A DXCoreFrameLowering.cpp204 unsigned Reg = CSI.getReg(); local
293 unsigned Reg = it->getReg(); local
319 unsigned Reg = it->getReg(); local
H A DXCoreRegisterInfo.cpp210 unsigned Reg = MI.getOperand(0).getReg(); local
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/macosx-10.10.1/llvmCore-3425.0.34/utils/TableGen/
H A DPseudoLoweringEmitter.cpp27 enum MapKind { Operand, Imm, Reg }; enumerator in enum:__anon10638::PseudoLoweringEmitter::OpData::MapKind
32 Record *Reg; // Physical register. member in union:__anon10638::PseudoLoweringEmitter::OpData::__anon10639
240 Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg; local
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/macosx-10.10.1/llvmCore-3425.0.34/include/llvm/CodeGen/
H A DCallingConvLower.h243 unsigned AllocateReg(unsigned Reg) { argument
250 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { argument
266 unsigned Reg = Regs[FirstUnalloc]; local
279 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; local
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/macosx-10.10.1/llvmCore-3425.0.34/include/llvm/MC/
H A DMCInst.h69 void setReg(unsigned Reg) { argument
111 static MCOperand CreateReg(unsigned Reg) { argument
/macosx-10.10.1/llvmCore-3425.0.34/lib/CodeGen/
H A DMachineInstr.cpp50 void MachineOperand::setReg(unsigned Reg) { argument
70 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, argument
80 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) { argument
130 ChangeToRegister(unsigned Reg, bool isDef, bool isImp, bool isKill, bool isDead, bool isUndef, bool isDebug) argument
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H A DMachineSink.cpp157 MachineSinking::AllUsesDominatedByBlock(unsigned Reg, argument
314 unsigned Reg = MO.getReg(); local
433 isProfitableToSinkTo(unsigned Reg, MachineInstr *MI, MachineBasicBlock *MBB, MachineBasicBlock *SuccToSinkTo) argument
489 unsigned Reg = MO.getReg(); local
612 unsigned Reg = MO.getReg(); local
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H A DPostRASchedulerList.cpp428 unsigned Reg = *I; local
441 unsigned Reg = *I; local
512 unsigned Reg = MO.getReg(); local
532 unsigned Reg = MO.getReg(); local
567 unsigned Reg = MO.getReg(); local
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H A DPrologEpilogInserter.cpp229 unsigned Reg = CSRegs[i]; local
247 unsigned Reg = I->getReg(); local
315 unsigned Reg = CSI[i].getReg(); local
342 unsigned Reg = CSI[i].getReg(); local
390 unsigned Reg = blockCSI[i].getReg(); local
441 unsigned Reg = blockCSI[i].getReg(); local
832 unsigned Reg = MO.getReg(); local
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/macosx-10.10.1/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp380 void ScheduleDAGFast::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, argument
423 static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, argument
438 static bool CheckForLiveRegDef(SUnit *SU, unsigned Reg, argument
492 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); local
562 unsigned Reg = LRegs[0]; local
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/macosx-10.10.1/llvmCore-3425.0.34/lib/ExecutionEngine/JIT/
H A DJITDwarfEmitter.cpp120 unsigned Reg = RI->getDwarfRegNum(Src.getReg(), true); local

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