1//===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the MipsMCCodeEmitter class. 11// 12//===----------------------------------------------------------------------===// 13// 14#define DEBUG_TYPE "mccodeemitter" 15#include "MCTargetDesc/MipsBaseInfo.h" 16#include "MCTargetDesc/MipsFixupKinds.h" 17#include "MCTargetDesc/MipsMCTargetDesc.h" 18#include "llvm/ADT/APFloat.h" 19#include "llvm/ADT/Statistic.h" 20#include "llvm/MC/MCCodeEmitter.h" 21#include "llvm/MC/MCExpr.h" 22#include "llvm/MC/MCInst.h" 23#include "llvm/MC/MCInstrInfo.h" 24#include "llvm/MC/MCRegisterInfo.h" 25#include "llvm/MC/MCSubtargetInfo.h" 26#include "llvm/Support/raw_ostream.h" 27 28using namespace llvm; 29 30namespace { 31class MipsMCCodeEmitter : public MCCodeEmitter { 32 MipsMCCodeEmitter(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION; 33 void operator=(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION; 34 const MCInstrInfo &MCII; 35 bool IsLittleEndian; 36 37public: 38 MipsMCCodeEmitter(const MCInstrInfo &mcii, bool IsLittle) : 39 MCII(mcii), IsLittleEndian(IsLittle) {} 40 41 ~MipsMCCodeEmitter() {} 42 43 void EmitByte(unsigned char C, raw_ostream &OS) const { 44 OS << (char)C; 45 } 46 47 void EmitInstruction(uint64_t Val, unsigned Size, raw_ostream &OS) const { 48 // Output the instruction encoding in little endian byte order. 49 for (unsigned i = 0; i < Size; ++i) { 50 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8; 51 EmitByte((Val >> Shift) & 0xff, OS); 52 } 53 } 54 55 void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 56 SmallVectorImpl<MCFixup> &Fixups) const; 57 58 // getBinaryCodeForInstr - TableGen'erated function for getting the 59 // binary encoding for an instruction. 60 uint64_t getBinaryCodeForInstr(const MCInst &MI, 61 SmallVectorImpl<MCFixup> &Fixups) const; 62 63 // getBranchJumpOpValue - Return binary encoding of the jump 64 // target operand. If the machine operand requires relocation, 65 // record the relocation and return zero. 66 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, 67 SmallVectorImpl<MCFixup> &Fixups) const; 68 69 // getBranchTargetOpValue - Return binary encoding of the branch 70 // target operand. If the machine operand requires relocation, 71 // record the relocation and return zero. 72 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, 73 SmallVectorImpl<MCFixup> &Fixups) const; 74 75 // getMachineOpValue - Return binary encoding of operand. If the machin 76 // operand requires relocation, record the relocation and return zero. 77 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 78 SmallVectorImpl<MCFixup> &Fixups) const; 79 80 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo, 81 SmallVectorImpl<MCFixup> &Fixups) const; 82 unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo, 83 SmallVectorImpl<MCFixup> &Fixups) const; 84 unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo, 85 SmallVectorImpl<MCFixup> &Fixups) const; 86 87}; // class MipsMCCodeEmitter 88} // namespace 89 90MCCodeEmitter *llvm::createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, 91 const MCRegisterInfo &MRI, 92 const MCSubtargetInfo &STI, 93 MCContext &Ctx) 94{ 95 return new MipsMCCodeEmitter(MCII, false); 96} 97 98MCCodeEmitter *llvm::createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, 99 const MCRegisterInfo &MRI, 100 const MCSubtargetInfo &STI, 101 MCContext &Ctx) 102{ 103 return new MipsMCCodeEmitter(MCII, true); 104} 105 106/// EncodeInstruction - Emit the instruction. 107/// Size the instruction (currently only 4 bytes 108void MipsMCCodeEmitter:: 109EncodeInstruction(const MCInst &MI, raw_ostream &OS, 110 SmallVectorImpl<MCFixup> &Fixups) const 111{ 112 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups); 113 114 // Check for unimplemented opcodes. 115 // Unfortunately in MIPS both NOT and SLL will come in with Binary == 0 116 // so we have to special check for them. 117 unsigned Opcode = MI.getOpcode(); 118 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary) 119 llvm_unreachable("unimplemented opcode in EncodeInstruction()"); 120 121 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 122 uint64_t TSFlags = Desc.TSFlags; 123 124 // Pseudo instructions don't get encoded and shouldn't be here 125 // in the first place! 126 if ((TSFlags & MipsII::FormMask) == MipsII::Pseudo) 127 llvm_unreachable("Pseudo opcode found in EncodeInstruction()"); 128 129 // For now all instructions are 4 bytes 130 int Size = 4; // FIXME: Have Desc.getSize() return the correct value! 131 132 EmitInstruction(Binary, Size, OS); 133} 134 135/// getBranchTargetOpValue - Return binary encoding of the branch 136/// target operand. If the machine operand requires relocation, 137/// record the relocation and return zero. 138unsigned MipsMCCodeEmitter:: 139getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, 140 SmallVectorImpl<MCFixup> &Fixups) const { 141 142 const MCOperand &MO = MI.getOperand(OpNo); 143 144 // If the destination is an immediate, we have nothing to do. 145 if (MO.isImm()) return MO.getImm(); 146 assert(MO.isExpr() && 147 "getBranchTargetOpValue expects only expressions or immediates"); 148 149 const MCExpr *Expr = MO.getExpr(); 150 Fixups.push_back(MCFixup::Create(0, Expr, 151 MCFixupKind(Mips::fixup_Mips_PC16))); 152 return 0; 153} 154 155/// getJumpTargetOpValue - Return binary encoding of the jump 156/// target operand. If the machine operand requires relocation, 157/// record the relocation and return zero. 158unsigned MipsMCCodeEmitter:: 159getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, 160 SmallVectorImpl<MCFixup> &Fixups) const { 161 162 const MCOperand &MO = MI.getOperand(OpNo); 163 // If the destination is an immediate, we have nothing to do. 164 if (MO.isImm()) return MO.getImm(); 165 assert(MO.isExpr() && 166 "getJumpTargetOpValue expects only expressions or an immediate"); 167 168 const MCExpr *Expr = MO.getExpr(); 169 Fixups.push_back(MCFixup::Create(0, Expr, 170 MCFixupKind(Mips::fixup_Mips_26))); 171 return 0; 172} 173 174/// getMachineOpValue - Return binary encoding of operand. If the machine 175/// operand requires relocation, record the relocation and return zero. 176unsigned MipsMCCodeEmitter:: 177getMachineOpValue(const MCInst &MI, const MCOperand &MO, 178 SmallVectorImpl<MCFixup> &Fixups) const { 179 if (MO.isReg()) { 180 unsigned Reg = MO.getReg(); 181 unsigned RegNo = getMipsRegisterNumbering(Reg); 182 return RegNo; 183 } else if (MO.isImm()) { 184 return static_cast<unsigned>(MO.getImm()); 185 } else if (MO.isFPImm()) { 186 return static_cast<unsigned>(APFloat(MO.getFPImm()) 187 .bitcastToAPInt().getHiBits(32).getLimitedValue()); 188 } 189 190 // MO must be an Expr. 191 assert(MO.isExpr()); 192 193 const MCExpr *Expr = MO.getExpr(); 194 MCExpr::ExprKind Kind = Expr->getKind(); 195 196 if (Kind == MCExpr::Binary) { 197 Expr = static_cast<const MCBinaryExpr*>(Expr)->getLHS(); 198 Kind = Expr->getKind(); 199 } 200 201 assert (Kind == MCExpr::SymbolRef); 202 203 Mips::Fixups FixupKind = Mips::Fixups(0); 204 205 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) { 206 default: llvm_unreachable("Unknown fixup kind!"); 207 break; 208 case MCSymbolRefExpr::VK_Mips_GPOFF_HI : 209 FixupKind = Mips::fixup_Mips_GPOFF_HI; 210 break; 211 case MCSymbolRefExpr::VK_Mips_GPOFF_LO : 212 FixupKind = Mips::fixup_Mips_GPOFF_LO; 213 break; 214 case MCSymbolRefExpr::VK_Mips_GOT_PAGE : 215 FixupKind = Mips::fixup_Mips_GOT_PAGE; 216 break; 217 case MCSymbolRefExpr::VK_Mips_GOT_OFST : 218 FixupKind = Mips::fixup_Mips_GOT_OFST; 219 break; 220 case MCSymbolRefExpr::VK_Mips_GOT_DISP : 221 FixupKind = Mips::fixup_Mips_GOT_DISP; 222 break; 223 case MCSymbolRefExpr::VK_Mips_GPREL: 224 FixupKind = Mips::fixup_Mips_GPREL16; 225 break; 226 case MCSymbolRefExpr::VK_Mips_GOT_CALL: 227 FixupKind = Mips::fixup_Mips_CALL16; 228 break; 229 case MCSymbolRefExpr::VK_Mips_GOT16: 230 FixupKind = Mips::fixup_Mips_GOT_Global; 231 break; 232 case MCSymbolRefExpr::VK_Mips_GOT: 233 FixupKind = Mips::fixup_Mips_GOT_Local; 234 break; 235 case MCSymbolRefExpr::VK_Mips_ABS_HI: 236 FixupKind = Mips::fixup_Mips_HI16; 237 break; 238 case MCSymbolRefExpr::VK_Mips_ABS_LO: 239 FixupKind = Mips::fixup_Mips_LO16; 240 break; 241 case MCSymbolRefExpr::VK_Mips_TLSGD: 242 FixupKind = Mips::fixup_Mips_TLSGD; 243 break; 244 case MCSymbolRefExpr::VK_Mips_TLSLDM: 245 FixupKind = Mips::fixup_Mips_TLSLDM; 246 break; 247 case MCSymbolRefExpr::VK_Mips_DTPREL_HI: 248 FixupKind = Mips::fixup_Mips_DTPREL_HI; 249 break; 250 case MCSymbolRefExpr::VK_Mips_DTPREL_LO: 251 FixupKind = Mips::fixup_Mips_DTPREL_LO; 252 break; 253 case MCSymbolRefExpr::VK_Mips_GOTTPREL: 254 FixupKind = Mips::fixup_Mips_GOTTPREL; 255 break; 256 case MCSymbolRefExpr::VK_Mips_TPREL_HI: 257 FixupKind = Mips::fixup_Mips_TPREL_HI; 258 break; 259 case MCSymbolRefExpr::VK_Mips_TPREL_LO: 260 FixupKind = Mips::fixup_Mips_TPREL_LO; 261 break; 262 case MCSymbolRefExpr::VK_Mips_HIGHER: 263 FixupKind = Mips::fixup_Mips_HIGHER; 264 break; 265 case MCSymbolRefExpr::VK_Mips_HIGHEST: 266 FixupKind = Mips::fixup_Mips_HIGHEST; 267 break; 268 } // switch 269 270 Fixups.push_back(MCFixup::Create(0, MO.getExpr(), MCFixupKind(FixupKind))); 271 272 // All of the information is in the fixup. 273 return 0; 274} 275 276/// getMemEncoding - Return binary encoding of memory related operand. 277/// If the offset operand requires relocation, record the relocation. 278unsigned 279MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo, 280 SmallVectorImpl<MCFixup> &Fixups) const { 281 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0. 282 assert(MI.getOperand(OpNo).isReg()); 283 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16; 284 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups); 285 286 return (OffBits & 0xFFFF) | RegBits; 287} 288 289unsigned 290MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo, 291 SmallVectorImpl<MCFixup> &Fixups) const { 292 assert(MI.getOperand(OpNo).isImm()); 293 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups); 294 return SizeEncoding - 1; 295} 296 297// FIXME: should be called getMSBEncoding 298// 299unsigned 300MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo, 301 SmallVectorImpl<MCFixup> &Fixups) const { 302 assert(MI.getOperand(OpNo-1).isImm()); 303 assert(MI.getOperand(OpNo).isImm()); 304 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups); 305 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups); 306 307 return Position + Size - 1; 308} 309 310#include "MipsGenMCCodeEmitter.inc" 311 312