1//===- TargetRegisterInfo.cpp - Target Register Information Implementation ===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the TargetRegisterInfo interface. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetMachine.h" 15#include "llvm/Target/TargetRegisterInfo.h" 16#include "llvm/ADT/BitVector.h" 17#include "llvm/Support/raw_ostream.h" 18 19using namespace llvm; 20 21TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 22 regclass_iterator RCB, regclass_iterator RCE, 23 const char *const *SRINames, 24 const unsigned *SRILaneMasks) 25 : InfoDesc(ID), SubRegIndexNames(SRINames), 26 SubRegIndexLaneMasks(SRILaneMasks), 27 RegClassBegin(RCB), RegClassEnd(RCE) { 28} 29 30TargetRegisterInfo::~TargetRegisterInfo() {} 31 32void PrintReg::print(raw_ostream &OS) const { 33 if (!Reg) 34 OS << "%noreg"; 35 else if (TargetRegisterInfo::isStackSlot(Reg)) 36 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg); 37 else if (TargetRegisterInfo::isVirtualRegister(Reg)) 38 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg); 39 else if (TRI && Reg < TRI->getNumRegs()) 40 OS << '%' << TRI->getName(Reg); 41 else 42 OS << "%physreg" << Reg; 43 if (SubIdx) { 44 if (TRI) 45 OS << ':' << TRI->getSubRegIndexName(SubIdx); 46 else 47 OS << ":sub(" << SubIdx << ')'; 48 } 49} 50 51void PrintRegUnit::print(raw_ostream &OS) const { 52 // Generic printout when TRI is missing. 53 if (!TRI) { 54 OS << "Unit~" << Unit; 55 return; 56 } 57 58 // Check for invalid register units. 59 if (Unit >= TRI->getNumRegUnits()) { 60 OS << "BadUnit~" << Unit; 61 return; 62 } 63 64 // Normal units have at least one root. 65 MCRegUnitRootIterator Roots(Unit, TRI); 66 assert(Roots.isValid() && "Unit has no roots."); 67 OS << TRI->getName(*Roots); 68 for (++Roots; Roots.isValid(); ++Roots) 69 OS << '~' << TRI->getName(*Roots); 70} 71 72/// getAllocatableClass - Return the maximal subclass of the given register 73/// class that is alloctable, or NULL. 74const TargetRegisterClass * 75TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { 76 if (!RC || RC->isAllocatable()) 77 return RC; 78 79 const unsigned *SubClass = RC->getSubClassMask(); 80 for (unsigned Base = 0, BaseE = getNumRegClasses(); 81 Base < BaseE; Base += 32) { 82 unsigned Idx = Base; 83 for (unsigned Mask = *SubClass++; Mask; Mask >>= 1) { 84 unsigned Offset = CountTrailingZeros_32(Mask); 85 const TargetRegisterClass *SubRC = getRegClass(Idx + Offset); 86 if (SubRC->isAllocatable()) 87 return SubRC; 88 Mask >>= Offset; 89 Idx += Offset + 1; 90 } 91 } 92 return NULL; 93} 94 95/// getMinimalPhysRegClass - Returns the Register Class of a physical 96/// register of the given type, picking the most sub register class of 97/// the right type that contains this physreg. 98const TargetRegisterClass * 99TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const { 100 assert(isPhysicalRegister(reg) && "reg must be a physical register"); 101 102 // Pick the most sub register class of the right type that contains 103 // this physreg. 104 const TargetRegisterClass* BestRC = 0; 105 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){ 106 const TargetRegisterClass* RC = *I; 107 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) && 108 (!BestRC || BestRC->hasSubClass(RC))) 109 BestRC = RC; 110 } 111 112 assert(BestRC && "Couldn't find the register class"); 113 return BestRC; 114} 115 116/// getAllocatableSetForRC - Toggle the bits that represent allocatable 117/// registers for the specific register class. 118static void getAllocatableSetForRC(const MachineFunction &MF, 119 const TargetRegisterClass *RC, BitVector &R){ 120 assert(RC->isAllocatable() && "invalid for nonallocatable sets"); 121 ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF); 122 for (unsigned i = 0; i != Order.size(); ++i) 123 R.set(Order[i]); 124} 125 126BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, 127 const TargetRegisterClass *RC) const { 128 BitVector Allocatable(getNumRegs()); 129 if (RC) { 130 // A register class with no allocatable subclass returns an empty set. 131 const TargetRegisterClass *SubClass = getAllocatableClass(RC); 132 if (SubClass) 133 getAllocatableSetForRC(MF, SubClass, Allocatable); 134 } else { 135 for (TargetRegisterInfo::regclass_iterator I = regclass_begin(), 136 E = regclass_end(); I != E; ++I) 137 if ((*I)->isAllocatable()) 138 getAllocatableSetForRC(MF, *I, Allocatable); 139 } 140 141 // Mask out the reserved registers 142 BitVector Reserved = getReservedRegs(MF); 143 Allocatable &= Reserved.flip(); 144 145 return Allocatable; 146} 147 148static inline 149const TargetRegisterClass *firstCommonClass(const uint32_t *A, 150 const uint32_t *B, 151 const TargetRegisterInfo *TRI) { 152 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32) 153 if (unsigned Common = *A++ & *B++) 154 return TRI->getRegClass(I + CountTrailingZeros_32(Common)); 155 return 0; 156} 157 158const TargetRegisterClass * 159TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A, 160 const TargetRegisterClass *B) const { 161 // First take care of the trivial cases. 162 if (A == B) 163 return A; 164 if (!A || !B) 165 return 0; 166 167 // Register classes are ordered topologically, so the largest common 168 // sub-class it the common sub-class with the smallest ID. 169 return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this); 170} 171 172const TargetRegisterClass * 173TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, 174 const TargetRegisterClass *B, 175 unsigned Idx) const { 176 assert(A && B && "Missing register class"); 177 assert(Idx && "Bad sub-register index"); 178 179 // Find Idx in the list of super-register indices. 180 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI) 181 if (RCI.getSubReg() == Idx) 182 // The bit mask contains all register classes that are projected into B 183 // by Idx. Find a class that is also a sub-class of A. 184 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this); 185 return 0; 186} 187 188const TargetRegisterClass *TargetRegisterInfo:: 189getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, 190 const TargetRegisterClass *RCB, unsigned SubB, 191 unsigned &PreA, unsigned &PreB) const { 192 assert(RCA && SubA && RCB && SubB && "Invalid arguments"); 193 194 // Search all pairs of sub-register indices that project into RCA and RCB 195 // respectively. This is quadratic, but usually the sets are very small. On 196 // most targets like X86, there will only be a single sub-register index 197 // (e.g., sub_16bit projecting into GR16). 198 // 199 // The worst case is a register class like DPR on ARM. 200 // We have indices dsub_0..dsub_7 projecting into that class. 201 // 202 // It is very common that one register class is a sub-register of the other. 203 // Arrange for RCA to be the larger register so the answer will be found in 204 // the first iteration. This makes the search linear for the most common 205 // case. 206 const TargetRegisterClass *BestRC = 0; 207 unsigned *BestPreA = &PreA; 208 unsigned *BestPreB = &PreB; 209 if (RCA->getSize() < RCB->getSize()) { 210 std::swap(RCA, RCB); 211 std::swap(SubA, SubB); 212 std::swap(BestPreA, BestPreB); 213 } 214 215 // Also terminate the search one we have found a register class as small as 216 // RCA. 217 unsigned MinSize = RCA->getSize(); 218 219 for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) { 220 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); 221 for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) { 222 // Check if a common super-register class exists for this index pair. 223 const TargetRegisterClass *RC = 224 firstCommonClass(IA.getMask(), IB.getMask(), this); 225 if (!RC || RC->getSize() < MinSize) 226 continue; 227 228 // The indexes must compose identically: PreA+SubA == PreB+SubB. 229 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); 230 if (FinalA != FinalB) 231 continue; 232 233 // Is RC a better candidate than BestRC? 234 if (BestRC && RC->getSize() >= BestRC->getSize()) 235 continue; 236 237 // Yes, RC is the smallest super-register seen so far. 238 BestRC = RC; 239 *BestPreA = IA.getSubReg(); 240 *BestPreB = IB.getSubReg(); 241 242 // Bail early if we reached MinSize. We won't find a better candidate. 243 if (BestRC->getSize() == MinSize) 244 return BestRC; 245 } 246 } 247 return BestRC; 248} 249