Lines Matching defs:Reg
210 unsigned Reg = MI.getOperand(0).getReg();
213 assert(XCore::GRRegsRegClass.contains(Reg) && "Unexpected register operand");
229 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
235 .addReg(Reg, getKillRegState(isKill))
240 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
250 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
256 .addReg(Reg, getKillRegState(isKill))
261 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
279 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
285 .addReg(Reg, getKillRegState(isKill))
290 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)