| /freebsd-11.0-release/contrib/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86AsmParser.cpp | 447 void onRegister(unsigned Reg) { argument
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| /freebsd-11.0-release/contrib/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 1044 unsigned Reg = getRegForValue(RV); local
1109 unsigned Reg = X86MFInfo->getSRetReturnReg(); local
2252 unsigned Reg; local
2612 static const unsigned Reg[] = { X86::AL, X86::AX, X86::EAX, X86::RAX }; local
2703 unsigned Reg = getRegForValue(Op); local
3265 unsigned Reg = getRegForValue(I->getOperand(0)); local
3285 unsigned Reg = getRegForValue(I->getOperand(0)); local
[all...] |
| H A D | X86ISelDAGToDAG.cpp | 98 void setBaseReg(SDValue Reg) { argument
1246 SDValue Reg; local
2802 SDValue Reg = N0.getNode()->getOperand(0); local
2838 SDValue Reg = N0.getNode()->getOperand(0); local
2875 SDValue Reg = N0.getNode()->getOperand(0); local
2898 SDValue Reg = N0.getNode()->getOperand(0); local
[all...] |
| H A D | X86InstrInfo.cpp | 2235 unsigned Reg; local
2257 unsigned Reg; local
4243 static bool isHReg(unsigned Reg) { argument
4289 static bool MaskRegClassContains(unsigned Reg) { argument
4297 GRRegClassContains(unsigned Reg) argument
4406 int Reg = FromEFLAGS ? DestReg : SrcReg; local
4496 getLoadStoreRegOpcode(unsigned Reg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI, bool load) argument
5240 unsigned Reg = MO.getReg(); local
5272 unsigned Reg = MIB->getOperand(0).getReg(); local
5290 Expand2AddrKreg(MachineInstrBuilder &MIB, const MCInstrDesc &Desc, unsigned Reg) argument
5302 unsigned Reg = MIB->getOperand(0).getReg(); local
5322 unsigned Reg = MIB->getOperand(0).getReg(); local
5764 unsigned Reg = MO.getReg(); local
5870 unsigned Reg = MI->getOperand(OpNum).getReg(); local
6136 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument
[all...] |
| H A D | X86ISelLowering.cpp | 2752 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); local
2793 unsigned Reg = FuncInfo->getSRetReturnReg(); local
3867 unsigned Reg = VA.getLocReg(); local
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 57 unsigned Reg; member in union:__anon2694::final::Address::__anon2696
74 void setReg(unsigned Reg) { argument
82 void setOffsetReg(unsigned Reg) { argument
700 unsigned Reg = getRegForValue(LHS); local
711 unsigned Reg = getRegForValue(Src); local
772 unsigned Reg = getRegForValue(Src); local
798 unsigned Reg = getRegForValue(LHS); local
832 unsigned Reg = getRegForValue(Src); local
841 unsigned Reg = getRegForValue(Obj); local
849 unsigned Reg = getRegForValue(Obj); local
1952 unsigned Reg = lookUpRegForValue(IntExtVal); local
3106 unsigned Reg = constrainOperandRegClass(II, Addr.getReg(), 0); local
3683 unsigned Reg = getRegForValue(RV); local
4327 unsigned Reg = lookUpRegForValue(LI); local
[all...] |
| H A D | AArch64ISelLowering.cpp | 2453 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); local
4361 unsigned Reg = StringSwitch<unsigned>(RegName) local
4388 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass); local
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| /freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 250 struct RegOp Reg; member in union:__anon2707::AArch64Operand::__anon2708
1184 uint32_t Reg = RI->getRegClass(AArch64::GPR32RegClassID).getRegister( local
1821 unsigned Reg = getVectorListStart(); local
2845 int64_t Reg = tryMatchVectorRegister(Kind, false); local
3025 int64_t Reg = tryMatchVectorRegister(NextKind, true); local
3046 int64_t Reg = tryMatchVectorRegister(NextKind, true); local
3995 unsigned Reg = getXRegFromWReg(Op.getReg()); local
4010 unsigned Reg = getXRegFromWReg(Op.getReg()); local
4026 unsigned Reg = getWRegFromXReg(Op.getReg()); local
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 2857 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument
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| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 247 unsigned Reg = MO.getReg(); local
834 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg, argument
1719 unsigned Reg = CmpMI->getOperand(0).getReg(); local
1827 canFoldIntoMOVCC(unsigned Reg, const MachineRegisterInfo &MRI, const TargetInstrInfo *TII) argument
2636 FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const argument
3407 getBundledDefMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &DefIdx, unsigned &Dist) argument
3430 getBundledUseMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &UseIdx, unsigned &Dist) argument
3652 unsigned Reg = DefMO.getReg(); local
4089 unsigned Reg = MI->getOperand(0).getReg(); local
4462 unsigned Reg = MO.getReg(); local
4519 unsigned Reg = MO.getReg(); local
[all...] |
| H A D | ARMISelLowering.cpp | 1983 unsigned Reg = State->AllocateReg(GPRArgRegs); local
3032 unsigned Reg local
3263 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); local
4163 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32)); local
4190 unsigned Reg = StringSwitch<unsigned>(RegName) local
7503 unsigned Reg = SavedRegs[i]; local
7917 unsigned Reg = MRI.createVirtualRegister(&ARM::rGPRRegClass); local
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Transforms/Scalar/ |
| H A D | LoopStrengthReduce.cpp | 184 RegUseTracker::countRegister(const SCEV *Reg, size_t LUIdx) { argument
195 RegUseTracker::dropRegister(const SCEV *Reg, size_t LUIdx) { argument
925 RateRegister(const SCEV *Reg, SmallPtrSetImpl<const SCEV *> &Regs, const Loop *L, ScalarEvolution &SE, DominatorTree &DT) argument
973 RatePrimaryRegister(const SCEV *Reg, SmallPtrSetImpl<const SCEV *> &Regs, const Loop *L, ScalarEvolution &SE, DominatorTree &DT, SmallPtrSetImpl<const SCEV *> *LoserRegs) argument
3672 const SCEV *Reg = Use; // Make a copy for ExtractImmediate to modify. local
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 198 struct RegTy Reg; member in union:__anon2822::HexagonOperand::__anon2823
636 unsigned Reg = Check.getErrRegister(); local
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| /freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 107 static bool isIntRegForSubInst(unsigned Reg) { argument
113 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) { argument
187 unsigned Reg = MO.getReg(); local
891 unsigned Reg = MI->getOperand(0).getReg(); local
899 unsigned Reg = MI->getOperand(0).getReg(); local
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 2035 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); local
2391 unsigned Reg; local
2470 getNextIntArgReg(unsigned Reg) argument
3055 unsigned Reg = MipsFI->getSRetReturnReg(); local
3191 unsigned Reg = MipsFI->getSRetReturnReg(); local
3315 parsePhysicalReg(StringRef C, StringRef &Prefix, unsigned long long &Reg) argument
3341 unsigned long long Reg; local
3809 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); local
3949 unsigned Reg = StringSwitch<unsigned>(RegName) local
3955 unsigned Reg = StringSwitch<unsigned>(RegName) local
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 58 bool setATRegIndex(unsigned Reg) { argument
1059 int Reg = (*(RegList.List))[i]; local
1368 OS << Reg << " "; variable
4496 MipsOperand &Reg = static_cast<MipsOperand &>(*TmpOperands.back()); local
4577 unsigned Reg = Op.getGPR32Reg(); local
4835 const AsmToken &Reg = Parser.getTok(); local
5298 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Reg; local
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 30 inline static unsigned getWRegFromXReg(unsigned Reg) { argument
70 inline static unsigned getXRegFromWReg(unsigned Reg) { argument
110 static inline unsigned getBRegFromDReg(unsigned Reg) { argument
150 static inline unsigned getDRegFromBReg(unsigned Reg) { argument
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 87 void saveFPReg(int Reg) { FPReg = Reg; } argument
552 struct RegOp Reg; member in union:__anon2788::ARMOperand::__anon2789
2753 static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) { argument
3239 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); local
3286 getNextRegister(unsigned Reg) argument
3339 int Reg = tryParseRegister(); local
3523 int Reg = tryParseRegister(); local
3581 int Reg = tryParseRegister(); local
4519 int Reg = tryParseRegister(); local
4601 int Reg = tryParseRegister(); local
5962 checkLowRegisterList(const MCInst &Inst, unsigned OpNo, unsigned Reg, unsigned HiReg, bool &containsReg) argument
5979 listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) argument
8995 unsigned Reg; local
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 2016 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) : local
2893 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); local
11179 unsigned Reg = StringSwitch<unsigned>(RegName) local
|