Target/ARM/ARMBaseInstrInfo.cpp

247         unsigned Reg = MO.getReg();
249         LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
251           MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
253             LV->addVirtualRegisterDead(Reg, NewMI);
259             if (!NewMI->readsRegister(Reg))
261             LV->addVirtualRegisterKilled(Reg, NewMI);
834 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
838     return MIB.addReg(Reg, State);
840   if (TargetRegisterInfo::isPhysicalRegister(Reg))
841     return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
842   return MIB.addReg(Reg, State, SubIdx);
1267   for (const auto &Reg : ScratchRegs) {
1268     LDM.addReg(Reg, RegState::Define);
1269     STM.addReg(Reg, RegState::Kill);
1719             unsigned Reg = CmpMI->getOperand(0).getReg();
1723                 isARMLowRegister(Reg))
1827 static MachineInstr *canFoldIntoMOVCC(unsigned Reg,
1830   if (!TargetRegisterInfo::isVirtualRegister(Reg))
1832   if (!MRI.hasOneNonDBGUse(Reg))
1834   MachineInstr *MI = MRI.getVRegDef(Reg);
2637                                      MachineInstr *DefMI, unsigned Reg,
2647   if (!MRI->hasOneNonDBGUse(Reg))
2684     Commute = UseMI->getOperand(2).getReg() != Reg;
2738   unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
3408                                            const MachineInstr *MI, unsigned Reg,
3418     Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
3431                                            const MachineInstr *MI, unsigned Reg,
3442     Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
3652   unsigned Reg = DefMO.getReg();
3658     DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
3670                                                    Reg, NewUseIdx, UseAdj);
3679   if (Reg == ARM::CPSR) {
4089   unsigned Reg = MI->getOperand(0).getReg();
4094   BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg)
4098     MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4099     MIB.addReg(Reg, RegState::Kill).addImm(0);
4107   MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4108   MIB.addReg(Reg, RegState::Kill).addImm(0);
4462   unsigned Reg = MO.getReg();
4475     UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI);
4486   // If this instruction actually reads a value from Reg, there is no unwanted
4492   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4494     if (!MO.getSubReg() || MI->readsVirtualRegister(Reg))
4496   } else if (ARM::SPRRegClass.contains(Reg)) {
4498     unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
4519   unsigned Reg = MO.getReg();
4520   assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
4522   unsigned DReg = Reg;
4525   if (ARM::SPRRegClass.contains(Reg)) {
4526     DReg = ARM::D0 + (Reg - ARM::S0) / 2;
4527     assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
4602     InputReg.Reg = MOReg.getReg();
4622     BaseReg.Reg = MOBaseReg.getReg();
4625     InsertedReg.Reg = MOInsertedReg.getReg();