| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64CondBrTuning.cpp | 100 unsigned NewOpc = TII->convertToFlagSettingOpc(MI.getOpcode(), Is64Bit); local
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| H A D | AArch64AdvSIMDScalarPass.cpp | 292 unsigned NewOpc = getTransformOpcode(OldOpc); local
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| H A D | AArch64InstrInfo.cpp | 1237 unsigned NewOpc = convertToNonFlagSettingOpc(CmpInstr); local
1491 unsigned NewOpc = sForm(*MI); local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86EvexToVex.cpp | 147 static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc) { argument
257 unsigned NewOpc = I->VexOpcode; local
[all...] |
| H A D | X86FixupLEAs.cpp | 592 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); local
630 unsigned NewOpc = local
636 unsigned NewOpc = getADDriFromLEA(MI.getOpcode(), Offset); local
663 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); local
685 unsigned NewOpc local
[all...] |
| H A D | X86InstructionSelector.cpp | 530 unsigned NewOpc = getLoadStoreOp(Ty, RB, Opc, MemOp.getAlign()); local
572 unsigned NewOpc = getLeaOP(Ty, STI); local
623 unsigned NewOpc = getLeaOP(Ty, STI); local
655 unsigned NewOpc; local
[all...] |
| H A D | X86MCInstLower.cpp | 517 unsigned NewOpc; local
549 unsigned NewOpc; local
574 unsigned NewOpc; local
617 unsigned NewOpc; local
689 unsigned NewOpc; local
853 unsigned NewOpc; local
878 unsigned NewOpc; local
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenPredicate.cpp | 388 unsigned NewOpc = getPredForm(Opc); local
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| H A D | HexagonRDFOpt.cpp | 224 unsigned OpNum, NewOpc; local
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| H A D | HexagonCopyToCombine.cpp | 872 unsigned NewOpc; local
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| H A D | HexagonConstExtenders.cpp | 1567 unsigned NewOpc = Ex.Neg ? Hexagon::S4_subi_asl_ri local
1636 unsigned NewOpc = ExtOpc == Hexagon::C2_cmpgei ? Hexagon::C2_cmplt local
1806 unsigned NewOpc = ExtOpc == Hexagon::M2_naccii ? Hexagon::A2_sub local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiMemAluCombiner.cpp | 252 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); local
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUPostLegalizerCombiner.cpp | 213 unsigned NewOpc = AMDGPU::G_AMDGPU_CVT_F32_UBYTE0 + MatchInfo.ShiftOffset / 8; local
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| H A D | SIFoldOperands.cpp | 345 unsigned NewOpc = IsFMA ? local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsBranchExpansion.cpp | 337 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); local
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| H A D | MipsInstrInfo.cpp | 595 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, argument
[all...] |
| H A D | MipsInstructionSelector.cpp | 497 const unsigned NewOpc = selectLoadStoreOpCode(I, MRI); local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineLICM.cpp | 1346 unsigned NewOpc = local
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| H A D | TwoAddressInstructionPass.cpp | 1199 unsigned NewOpc = local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 668 unsigned NewOpc = Node->getOpcode(); local
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 901 unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize); local
1097 const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize); local
[all...] |
| H A D | ARMLoadStoreOptimizer.cpp | 1325 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); local
1457 unsigned NewOpc; local
[all...] |
| H A D | ARMConstantIslandPass.cpp | 1732 unsigned NewOpc = 0; local
1817 unsigned NewOpc = 0; member in struct:ImmCompare
[all...] |
| H A D | ARMExpandPseudoInsts.cpp | 2079 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; local
2121 unsigned NewOpc; local
2398 unsigned NewOpc = ARM::VLDMDIA; local
2429 unsigned NewOpc = ARM::VSTMDIA; local
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelDAGToDAG.cpp | 1342 unsigned NewOpc = 0; local
|