| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRegPressure.cpp | 97 inc(unsigned Reg, LaneBitmask PrevMask, LaneBitmask NewMask, const MachineRegisterInfo &MRI) argument
[all...] |
| H A D | SIModeRegister.cpp | 47 Status(unsigned NewMask, unsigned NewMode) : Mask(NewMask), Mode(NewMode) { argument
66 unsigned NewMask = (Mask & S.Mask) & (Mode ^ ~S.Mode); local
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| H A D | SIISelLowering.cpp | 8371 unsigned NewMask = LCC == ISD::SETO ? local
8465 uint32_t NewMask = (CLHS->getZExtValue() | CRHS->getZExtValue()) & MaxMask; local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterPressure.cpp | 50 increaseSetPressure(std::vector<unsigned> &CurrSetPressure, const MachineRegisterInfo &MRI, unsigned Reg, LaneBitmask PrevMask, LaneBitmask NewMask) argument
64 decreaseSetPressure(std::vector<unsigned> &CurrSetPressure, const MachineRegisterInfo &MRI, unsigned Reg, LaneBitmask PrevMask, LaneBitmask NewMask) argument
155 increaseRegPressure(unsigned RegUnit, LaneBitmask PreviousMask, LaneBitmask NewMask) argument
170 decreaseRegPressure(unsigned RegUnit, LaneBitmask PreviousMask, LaneBitmask NewMask) argument
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineShifts.cpp | 216 Constant *NewMask; local
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| H A D | InstCombineSimplifyDemanded.cpp | 299 APInt NewMask = ~(LHSKnown.One & RHSKnown.One & DemandedMask); local
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| H A D | InstCombineVectorOps.cpp | 844 Constant *NewMask = ConstantVector::get(NewMaskVec); local
893 Constant *NewMask = ConstantVector::get(NewMaskVec); local
[all...] |
| H A D | InstCombineAndOrXor.cpp | 280 unsigned NewMask; local
511 Value *NewMask = ConstantInt::get(BCst->getType(), BorD); local
690 APInt NewMask = BCst->getValue() & DCst->getValue(); local
703 APInt NewMask local
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 1648 SDValue NewMask = DAG.getConstant(0xff, DL, VT); local
1720 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, DL, VT); local
1886 SDValue NewMask = DAG.getConstant(Mask >> AMShiftAmt, DL, VT); local
4008 SDValue NewMask local
[all...] |
| H A D | X86InstrInfo.cpp | 6564 unsigned NewMask = 0; local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 4243 ArrayRef<int> NewMask = SV->getMask().slice(0, VT.getVectorNumElements()); local
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| H A D | LegalizeVectorTypes.cpp | 4071 SmallVector<int, 16> NewMask; local
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| H A D | DAGCombiner.cpp | 4762 SDValue NewMask = DAG.getConstant(AndMask.trunc(Size / 2), SL, HalfVT); local
11380 SmallVector<int, 8> NewMask; local
19168 SmallVector<int, 8> NewMask; local
19184 SmallVector<int, 8> NewMask; local
19306 SmallVector<int, 8> NewMask; local
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 286 unsigned NewMask = 0; local
334 unsigned NewMask = 0; local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13050 SmallVector<int, 16> NewMask; local
|