| /macosx-10.9.5/llvmCore-3425.0.33/lib/Transforms/IPO/ |
| H A D | IPConstantPropagation.cpp | 250 Instruction *Ins = cast<Instruction>(*I); local
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| H A D | PartialInlining.cpp | 93 BasicBlock::iterator Ins = newReturnBlock->begin(); local
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| /macosx-10.9.5/tcl-102/tcl_ext/mk4tcl/metakit/tests/ |
| H A D | tresize.cpp | 70 int CResizer::Ins(int pos_, int cnt_) { function in class:CResizer
[all...] |
| /macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/ |
| H A D | CallingConvLower.cpp | 67 CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, argument
155 void CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, argument
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| H A D | RegAllocGreedy.cpp | 707 unsigned Ins = 0; local
712 BC.Entry = SpillPlacement::MustSpill, ++Ins; local
714 BC.Entry = SpillPlacement::PrefSpill, ++Ins; local
722 BC.Exit = SpillPlacement::MustSpill, ++Ins; local
724 BC.Exit = SpillPlacement::PrefSpill, ++Ins; local
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| /macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Hexagon/ |
| H A D | HexagonCallingConvLower.cpp | 180 Hexagon_CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, argument
66 AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, Hexagon_CCAssignFn Fn, unsigned SretValueInRegs) argument
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| H A D | HexagonISelLowering.cpp | 379 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local
341 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const argument
801 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1589 IsEligibleForTailCallOptimization( SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument
[all...] |
| /macosx-10.9.5/llvmCore-3425.0.33/include/llvm/Transforms/Utils/ |
| H A D | SSAUpdaterImpl.h | 70 SSAUpdaterImpl(UpdaterT *U, AvailableValsTy *A, SmallVectorImpl<PhiT*> *Ins) argument
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| /macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 82 Ins, enumerator in enum:llvm::MipsISD::NodeType
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| H A D | MipsISelLowering.cpp | 2877 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local
3152 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
3245 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...] |
| /macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.cpp | 948 MachineBasicBlock::iterator Ins = MBB->begin(); local
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| /macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MBlaze/ |
| H A D | MBlazeISelLowering.cpp | 690 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local
843 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
873 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
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| /macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 275 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local
245 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
302 LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
440 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
566 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...] |
| /macosx-10.9.5/llvmCore-3425.0.33/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 448 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local
913 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
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| /macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 354 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local
148 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
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| /macosx-10.9.5/llvmCore-3425.0.33/utils/TableGen/ |
| H A D | CodeGenRegisters.h | 76 std::pair<CompMap::iterator, bool> Ins = local
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| H A D | CodeGenRegisters.cpp | 315 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*>::iterator Ins = local
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| /macosx-10.9.5/llvmCore-3425.0.33/include/llvm/TableGen/ |
| H A D | Record.h | 1577 bool Ins = Classes.insert(std::make_pair(R->getName(), R)).second; local
1582 bool Ins = Defs.insert(std::make_pair(R->getName(), R)).second; local
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| /macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 1903 SmallVector<ISD::InputArg, 32> Ins; local
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| /macosx-10.9.5/llvmCore-3425.0.33/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 883 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local
910 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1036 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1066 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1090 LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...] |
| /macosx-10.9.5/tcl-102/tcl_ext/tcllib/tcllib/modules/pt/ |
| H A D | pt_peg_to_param.tcl | [all...] |
| H A D | pt_peg_to_tclparam.tcl | [all...] |
| /macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CellSPU/ |
| H A D | SPUISelLowering.cpp | 1274 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local
1117 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
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| /macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 6689 SmallVector<ISD::InputArg, 16> Ins; local
[all...] |
| /macosx-10.9.5/llvmCore-3425.0.33/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 1712 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1729 LowerFormalArguments_32SVR4( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1947 LowerFormalArguments_Darwin_Or_64SVR4( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
2419 IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument
2840 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
2866 FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall, bool isVarArg, SelectionDAG &DAG, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue InFlag, SDValue Chain, SDValue &Callee, int SPDiff, unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins, SmallVectorImpl<SDValue> &InVals) const argument
2979 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local
3001 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
3214 LowerCall_Darwin_Or_64SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
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