Searched defs:DL (Results 201 - 225 of 440) sorted by relevance

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/freebsd-11-stable/sys/amd64/amd64/
H A Dbpf_jit_machdep.h85 #define DL 2 macro
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DFunctionComparator.cpp410 const DataLayout &DL = FnL->getParent()->getDataLayout(); local
672 const DataLayout &DL = FnL->getParent()->getDataLayout(); local
H A DPromoteMemoryToRegister.cpp863 static void updateForIncomingValueLocation(PHINode *PN, DebugLoc DL, argument
347 rewriteSingleStoreAlloca(AllocaInst *AI, AllocaInfo &Info, LargeBlockInfo &LBI, const DataLayout &DL, DominatorTree &DT, AssumptionCache *AC) argument
444 promoteSingleBlockAlloca(AllocaInst *AI, const AllocaInfo &Info, LargeBlockInfo &LBI, const DataLayout &DL, DominatorTree &DT, AssumptionCache *AC) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/
H A DExecutionEngine.h114 const DataLayout DL; member in class:llvm::ExecutionEngine
496 ExecutionEngine(DataLayout DL) : DL(std::move(DL)) {} argument
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h316 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, argument
323 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, argument
332 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const DebugLoc &DL, const MCInstrDesc &MCID, Register DestReg) argument
348 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::instr_iterator I, const DebugLoc &DL, const MCInstrDesc &MCID, Register DestReg) argument
358 BuildMI(MachineBasicBlock &BB, MachineInstr &I, const DebugLoc &DL, const MCInstrDesc &MCID, Register DestReg) argument
368 BuildMI(MachineBasicBlock &BB, MachineInstr *I, const DebugLoc &DL, const MCInstrDesc &MCID, Register DestReg) argument
377 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const DebugLoc &DL, const MCInstrDesc &MCID) argument
387 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::instr_iterator I, const DebugLoc &DL, const MCInstrDesc &MCID) argument
397 BuildMI(MachineBasicBlock &BB, MachineInstr &I, const DebugLoc &DL, const MCInstrDesc &MCID) argument
407 BuildMI(MachineBasicBlock &BB, MachineInstr *I, const DebugLoc &DL, const MCInstrDesc &MCID) argument
415 BuildMI(MachineBasicBlock *BB, const DebugLoc &DL, const MCInstrDesc &MCID) argument
423 BuildMI(MachineBasicBlock *BB, const DebugLoc &DL, const MCInstrDesc &MCID, Register DestReg) argument
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H A DSwitchLoweringUtils.h132 SDLoc DL; member in struct:llvm::SwitchCG::CaseBlock
292 const DataLayout *DL; member in class:llvm::SwitchCG::SwitchLowering
H A DAsmPrinter.h442 virtual void EmitXXStructor(const DataLayout &DL, const Constant *CV) { argument
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h46 DebugLoc DL; member in struct:llvm::MachineIRBuilderState
321 void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; } argument
H A DIRTranslator.h510 const DataLayout *DL; member in class:llvm::IRTranslator
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/Orc/
H A DCompileOnDemandLayer.h394 const DataLayout &DL = SrcM.getDataLayout(); local
570 static std::string mangle(StringRef Name, const DataLayout &DL) { argument
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/
H A DModule.h191 DataLayout DL; ///< DataLayout associated with the module member in class:llvm::Module
H A DDataLayout.h202 DataLayout(const DataLayout &DL) { *this = DL; } argument
206 DataLayout &operator=(const DataLayout &DL) { argument
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H A DValue.h593 Value *stripAndAccumulateConstantOffsets(const DataLayout &DL, APInt &Offset, argument
602 const Value *stripAndAccumulateInBoundsConstantOffsets(const DataLayout &DL, argument
607 Value *stripAndAccumulateInBoundsConstantOffsets(const DataLayout &DL, argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp119 void llvm::ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, argument
127 void llvm::computeValueLLTs(const DataLayout &DL, Typ argument
273 getNoopInput(const Value *V, SmallVectorImpl<unsigned> &ValLoc, unsigned &DataBits, const TargetLoweringBase &TLI, const DataLayout &DL) argument
354 slotOnlyDiscardsData(const Value *RetVal, const Value *CallVal, SmallVectorImpl<unsigned> &RetIndices, SmallVectorImpl<unsigned> &CallIndices, bool AllowDifferingSizes, const TargetLoweringBase &TLI, const DataLayout &DL) argument
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H A DInterleavedLoadCombinePass.cpp712 static bool compute(Value *V, VectorInfo &Result, const DataLayout &DL) { argument
731 computeFromBCI(BitCastInst *BCI, VectorInfo &Result, const DataLayout &DL) argument
786 computeFromSVI(ShuffleVectorInst *SVI, VectorInfo &Result, const DataLayout &DL) argument
868 computeFromLI(LoadInst *LI, VectorInfo &Result, const DataLayout &DL) argument
956 computePolynomialFromPointer(Value &Ptr, Polynomial &Result, Value *&BasePtr, const DataLayout &DL) argument
1053 findPattern( std::list<VectorInfo> &Candidates, std::list<VectorInfo> &InterleavedLoad, unsigned Factor, const DataLayout &DL) argument
1259 auto &DL = F.getParent()->getDataLayout(); local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUSubtarget.cpp498 const DataLayout &DL = F.getParent()->getDataLayout(); local
H A DR600ControlFlowFinalizer.cpp480 void EmitALUClause(MachineBasicBlock::iterator InsertPos, const DebugLoc &DL, argument
661 DebugLoc DL = MBB.findDebugLoc(MI); variable
468 EmitFetchClause(MachineBasicBlock::iterator InsertPos, const DebugLoc &DL, ClauseFile &Clause, unsigned &CfCount) argument
H A DAMDGPUPromoteAlloca.cpp84 const DataLayout *DL = nullptr; member in class:__anon2083::AMDGPUPromoteAlloca
648 const DataLayout &DL = Mod->getDataLayout(); local
762 const DataLayout &DL = Mod->getDataLayout(); local
H A DSIMemoryLegalizer.cpp720 DebugLoc DL = MI->getDebugLoc(); local
764 DebugLoc DL = MI->getDebugLoc(); local
858 DebugLoc DL = MI->getDebugLoc(); local
960 DebugLoc DL = MI->getDebugLoc(); local
1014 DebugLoc DL = MI->getDebugLoc(); local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.cpp638 DebugLoc DL; // Defaults to "unknown" local
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp54 DebugLoc DL; local
74 DebugLoc DL; local
34 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, const DebugLoc &DL, MCRegister DestinationRegister, MCRegister SourceRegister, bool KillSource) const argument
660 insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock, MachineBasicBlock *FalseBlock, ArrayRef<MachineOperand> Condition, const DebugLoc &DL, int *BytesAdded) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp203 const DataLayout &DL; member in class:__anon2321::MemDefsUses
495 MemDefsUses::MemDefsUses(const DataLayout &DL, const MachineFrameInfo *MFI_) argument
560 replaceWithCompactBranch(MachineBasicBlock &MBB, Iter Branch, const DebugLoc &DL) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallLowering.cpp272 auto &DL = F.getParent()->getDataLayout(); local
422 auto &DL = F.getParent()->getDataLayout(); local
219 splitToValueTypes( const ArgInfo &OrigArg, SmallVectorImpl<ArgInfo> &SplitArgs, const DataLayout &DL, MachineRegisterInfo &MRI, CallingConv::ID CallConv) const argument
926 auto &DL = F.getParent()->getDataLayout(); local
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H A DAArch64StackTagging.cpp73 const DataLayout *DL; member in class:__anon2048::InitializerBuilder
90 InitializerBuilder(uint64_t Size, const DataLayout *DL, Value *BasePtr, argument
108 bool addStore(uint64_t Offset, StoreInst *SI, const DataLayout *DL) { argument
310 const DataLayout *DL; member in class:__anon2048::AArch64StackTagging
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp39 static void fail(const SDLoc &DL, SelectionDAG &DAG, const Twine &Msg) { argument
45 static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *Msg, argument
206 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
407 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, SelectionDAG &DAG) const argument
454 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
570 DebugLoc DL = MI.getDebugLoc(); local
620 DebugLoc DL = MI.getDebugLoc(); local
759 getScalarShiftAmountTy(const DataLayout &DL, EVT VT) const argument
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