| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb2InstrInfo.cpp | 230 emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
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| H A D | ThumbRegisterInfo.cpp | 123 emitThumbRegPlusImmInReg( MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags = MachineInstr::NoFlags) argument
185 emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags) argument
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| H A D | ARMBaseRegisterInfo.cpp | 663 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, argument
637 materializeFrameBaseRegister(MachineBasicBlock *MBB, Register BaseReg, int FrameIdx, int64_t Offset) const argument
691 isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const argument
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| H A D | Thumb2SizeReduction.cpp | 499 Register BaseReg = MI->getOperand(0).getReg(); local
537 Register BaseReg = MI->getOperand(1).getReg(); local
550 Register BaseReg = MI->getOperand(1).getReg(); local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64StorePairSuppress.cpp | 156 Register BaseReg = BaseOp->getReg(); local
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| H A D | AArch64FalkorHWPFFix.cpp | 217 Register BaseReg; member in struct:__anon3848::LoadInfo
646 Register BaseReg = MI.getOperand(BaseRegIdx).getReg(); local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixupVectorISel.cpp | 175 unsigned BaseReg = 0; local
85 findSRegBaseAndIndex(MachineOperand *Op, unsigned &BaseReg, unsigned &IndexReg, MachineRegisterInfo &MRI, const SIRegisterInfo *TRI) argument
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCRegisterInfo.cpp | 46 unsigned BaseReg = FrameReg; local
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| H A D | ARCOptAddrMode.cpp | 287 Register BaseReg = Ldst->getOperand(BasePos).getReg(); local
449 Register BaseReg = Ldst.getOperand(BasePos).getReg(); local
342 canFixPastUses(const ArrayRef<MachineInstr *> &Uses, MachineOperand &Incr, unsigned BaseReg) argument
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86ATTInstPrinter.cpp | 387 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); local
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| H A D | X86IntelInstPrinter.cpp | 345 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); local
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| H A D | X86MCCodeEmitter.cpp | 392 unsigned BaseReg = Base.getReg(); local
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| H A D | X86MCTargetDesc.cpp | 542 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InsertPrefetch.cpp | 82 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); local
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| H A D | X86AsmPrinter.cpp | 288 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); local
353 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); local
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| H A D | X86SelectionDAGInfo.cpp | 40 Register BaseReg = TRI->getBaseRegister(); local
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| H A D | X86FixupLEAs.cpp | 383 Register BaseReg = Base.getReg(); local
563 Register BaseReg = Base.getReg(); local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LocalStackSlotAllocation.cpp | 271 lookupCandidateBaseReg(unsigned BaseReg, argument
345 unsigned BaseReg = 0; local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 233 unsigned BaseReg = MI->getOperand(0).getReg(); local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiMemAluCombiner.cpp | 374 BaseReg = MBBIter->getOperand(1).getReg(); local
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| /freebsd-13-stable/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/ |
| H A D | Store.cpp | 295 const MemRegion *BaseReg = MRMgr.getCXXBaseObjectRegion( local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonStoreWidening.cpp | 242 unsigned BaseReg = getBaseAddressRegister(BaseStore); local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 583 getMemOperandWithOffsetWidth( const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const argument
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 131 unsigned BaseReg; member in struct:__anon4170::LanaiOperand::MemOp
624 MorphToMemRegReg(unsigned BaseReg, std::unique_ptr<LanaiOperand> Op, argument
636 MorphToMemRegImm(unsigned BaseReg, std::unique_ptr<LanaiOperand> Op, argument
909 unsigned BaseReg local
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