Lines Matching defs:BaseReg
167 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg);
171 if (STI.hasFeature(X86::Mode16Bit) && BaseReg.getReg() == 0 && Disp.isImm() &&
174 if ((BaseReg.getReg() != 0 &&
175 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
186 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg);
189 if ((BaseReg.getReg() != 0 &&
190 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
194 if (BaseReg.getReg() == X86::EIP) {
208 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg);
211 if ((BaseReg.getReg() != 0 &&
212 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
392 unsigned BaseReg = Base.getReg();
396 if (BaseReg == X86::RIP ||
397 BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode
448 unsigned BaseRegNo = BaseReg ? getX86RegNum(Base) : -1U;
453 if (BaseReg) {
501 // There is no BaseReg; this is the plain [disp16] case.
511 // If no BaseReg, issue a RIP relative instruction only if the MCE can
523 (!STI.hasFeature(X86::Mode64Bit) || BaseReg != 0)) {
525 if (BaseReg == 0) { // [disp32] in X86-32 mode
590 if (BaseReg == 0) {
623 if (BaseReg == 0) {