Lines Matching defs:BaseReg
383 Register BaseReg = Base.getReg();
392 if (BaseReg != 0)
393 BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);
402 if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 &&
403 (DestReg == BaseReg || DestReg == IndexReg)) {
405 if (DestReg != BaseReg)
406 std::swap(BaseReg, IndexReg);
411 .addReg(BaseReg).addReg(IndexReg)
416 .addReg(BaseReg).addReg(IndexReg);
418 } else if (DestReg == BaseReg && IndexReg == 0) {
432 .addReg(BaseReg).addReg(Base.getReg(), RegState::Implicit);
435 .addReg(BaseReg);
442 .addReg(BaseReg).addImm(Disp.getImm())
446 .addReg(BaseReg).addImm(Disp.getImm());
563 Register BaseReg = Base.getReg();
567 if (BaseReg != 0)
568 BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);
574 bool IsInefficientBase = isInefficientLEAReg(BaseReg);
579 if (IsInefficientBase && DestReg == BaseReg && !IsScale1)
591 if (IsScale1 && (DestReg == BaseReg || DestReg == IndexReg)) {
593 if (DestReg != BaseReg)
594 std::swap(BaseReg, IndexReg);
599 .addReg(BaseReg)
605 .addReg(BaseReg)
650 assert(DestReg != BaseReg && "DestReg == BaseReg should be handled already!");
659 bool BIK = Base.isKill() && BaseReg != IndexReg;
660 TII->copyPhysReg(MBB, MI, MI.getDebugLoc(), DestReg, BaseReg, BIK);