| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/NVPTX/ |
| H A D | NVPTXSubtarget.cpp | 35 NVPTXSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool is64Bit) argument
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| H A D | NVPTXTargetMachine.cpp | 63 NVPTXTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions& Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
83 NVPTXTargetMachine32(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
93 NVPTXTargetMachine64(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/PowerPC/InstPrinter/ |
| H A D | PPCInstPrinter.cpp | 26 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { argument
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| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCELFObjectWriter.cpp | 98 MCObjectWriter *llvm::createPPCELFObjectWriter(raw_ostream &OS, argument
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| H A D | PPCMCCodeEmitter.cpp | 62 void EncodeInstruction(const MCInst &MI, raw_ostream &OS, argument
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| H A D | PPCMCTargetDesc.cpp | 54 createPPCMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) argument
96 createMCStreamer(const Target &T, StringRef TT, MCContext &Ctx, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *Emitter, bool RelaxAll, bool NoExecStack) argument
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| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/PowerPC/ |
| H A D | PPCCTRLoops.cpp | 170 void print(raw_ostream &OS, const TargetMachine *TM = 0) const { argument
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| H A D | PPCRegisterInfo.cpp | 267 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, argument
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| H A D | PPCSubtarget.cpp | 29 PPCSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool is64Bit) argument
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| H A D | PPCTargetMachine.cpp | 35 PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument
55 PPC32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
65 PPC64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Sparc/MCTargetDesc/ |
| H A D | SparcMCTargetDesc.cpp | 46 createSparcMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) argument
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| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Sparc/ |
| H A D | SparcSubtarget.cpp | 26 SparcSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool is64Bit) argument
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| H A D | SparcTargetMachine.cpp | 28 SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
78 SparcV8TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
90 SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ |
| H A D | TargetMachine.cpp | 45 TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options) argument
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| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/X86/InstPrinter/ |
| H A D | X86ATTInstPrinter.cpp | 35 void X86ATTInstPrinter::printRegName(raw_ostream &OS, argument
40 void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, argument
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| H A D | X86InstComments.cpp | 29 void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, argument
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| H A D | X86IntelInstPrinter.cpp | 30 void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { argument
34 void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, argument
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| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/X86/MCTargetDesc/ |
| H A D | X86AsmBackend.cpp | 344 const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section); local
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| H A D | X86BaseInfo.h | 335 XD = 11 << Op0Shift, XS = 12 << Op0Shift, enumerator in enum:llvm::X86II::__anon10298
422 FS = 1 << SegOvrShift, enumerator in enum:llvm::X86II::__anon10298
423 GS = 2 << SegOvrShift, enumerator in enum:llvm::X86II::__anon10298
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| H A D | X86ELFObjectWriter.cpp | 218 MCObjectWriter *llvm::createX86ELFObjectWriter(raw_ostream &OS, argument
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| H A D | X86MCCodeEmitter.cpp | 297 EmitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField, uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups) const argument
412 unsigned SS = SSTable[Scale.getImm()]; local
957 EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups) const argument
1203 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS); local
[all...] |
| H A D | X86MCTargetDesc.cpp | 48 std::string FS; local
332 createX86MCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) argument
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| H A D | X86MachObjectWriter.cpp | 578 MCObjectWriter *llvm::createX86MachObjectWriter(raw_ostream &OS, argument
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| H A D | X86WinCOFFObjectWriter.cpp | 61 MCObjectWriter *llvm::createX86WinCOFFObjectWriter(raw_ostream &OS, argument
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| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/X86/ |
| H A D | X86CodeEmitter.cpp | 298 void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES, argument
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