1//===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file includes code for rendering MCInst instances as AT&T-style
11// assembly.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "asm-printer"
16#include "X86ATTInstPrinter.h"
17#include "X86InstComments.h"
18#include "MCTargetDesc/X86BaseInfo.h"
19#include "MCTargetDesc/X86MCTargetDesc.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCAsmInfo.h"
22#include "llvm/MC/MCExpr.h"
23#include "llvm/MC/MCInstrInfo.h"
24#include "llvm/MC/MCRegisterInfo.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/Format.h"
27#include "llvm/Support/FormattedStream.h"
28#include <map>
29using namespace llvm;
30
31// Include the auto-generated portion of the assembly writer.
32#define PRINT_ALIAS_INSTR
33#include "X86GenAsmWriter.inc"
34
35void X86ATTInstPrinter::printRegName(raw_ostream &OS,
36                                     unsigned RegNo) const {
37  OS << '%' << getRegisterName(RegNo);
38}
39
40void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
41                                  StringRef Annot) {
42  const MCInstrDesc &Desc = MII.get(MI->getOpcode());
43  uint64_t TSFlags = Desc.TSFlags;
44
45  if (TSFlags & X86II::LOCK)
46    OS << "\tlock\n";
47
48  // Try to print any aliases first.
49  if (!printAliasInstr(MI, OS))
50    printInstruction(MI, OS);
51
52  // Next always print the annotation.
53  printAnnotation(OS, Annot);
54
55  // If verbose assembly is enabled, we can print some informative comments.
56  if (CommentStream)
57    EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
58}
59
60void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
61                                   raw_ostream &O) {
62  switch (MI->getOperand(Op).getImm()) {
63  default: llvm_unreachable("Invalid ssecc argument!");
64  case    0: O << "eq"; break;
65  case    1: O << "lt"; break;
66  case    2: O << "le"; break;
67  case    3: O << "unord"; break;
68  case    4: O << "neq"; break;
69  case    5: O << "nlt"; break;
70  case    6: O << "nle"; break;
71  case    7: O << "ord"; break;
72  case    8: O << "eq_uq"; break;
73  case    9: O << "nge"; break;
74  case  0xa: O << "ngt"; break;
75  case  0xb: O << "false"; break;
76  case  0xc: O << "neq_oq"; break;
77  case  0xd: O << "ge"; break;
78  case  0xe: O << "gt"; break;
79  case  0xf: O << "true"; break;
80  case 0x10: O << "eq_os"; break;
81  case 0x11: O << "lt_oq"; break;
82  case 0x12: O << "le_oq"; break;
83  case 0x13: O << "unord_s"; break;
84  case 0x14: O << "neq_us"; break;
85  case 0x15: O << "nlt_uq"; break;
86  case 0x16: O << "nle_uq"; break;
87  case 0x17: O << "ord_s"; break;
88  case 0x18: O << "eq_us"; break;
89  case 0x19: O << "nge_uq"; break;
90  case 0x1a: O << "ngt_uq"; break;
91  case 0x1b: O << "false_os"; break;
92  case 0x1c: O << "neq_os"; break;
93  case 0x1d: O << "ge_oq"; break;
94  case 0x1e: O << "gt_oq"; break;
95  case 0x1f: O << "true_us"; break;
96  }
97}
98
99/// printPCRelImm - This is used to print an immediate value that ends up
100/// being encoded as a pc-relative value (e.g. for jumps and calls).  These
101/// print slightly differently than normal immediates.  For example, a $ is not
102/// emitted.
103void X86ATTInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
104                                      raw_ostream &O) {
105  const MCOperand &Op = MI->getOperand(OpNo);
106  if (Op.isImm())
107    O << Op.getImm();
108  else {
109    assert(Op.isExpr() && "unknown pcrel immediate operand");
110    // If a symbolic branch target was added as a constant expression then print
111    // that address in hex.
112    const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
113    int64_t Address;
114    if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
115      O << "0x";
116      O.write_hex(Address);
117    }
118    else {
119      // Otherwise, just print the expression.
120      O << *Op.getExpr();
121    }
122  }
123}
124
125void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
126                                     raw_ostream &O) {
127  const MCOperand &Op = MI->getOperand(OpNo);
128  if (Op.isReg()) {
129    O << '%' << getRegisterName(Op.getReg());
130  } else if (Op.isImm()) {
131    // Print X86 immediates as signed values.
132    O << '$' << (int64_t)Op.getImm();
133
134    if (CommentStream && (Op.getImm() > 255 || Op.getImm() < -256))
135      *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Op.getImm());
136
137  } else {
138    assert(Op.isExpr() && "unknown operand kind in printOperand");
139    O << '$' << *Op.getExpr();
140  }
141}
142
143void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
144                                          raw_ostream &O) {
145  const MCOperand &BaseReg  = MI->getOperand(Op);
146  const MCOperand &IndexReg = MI->getOperand(Op+2);
147  const MCOperand &DispSpec = MI->getOperand(Op+3);
148  const MCOperand &SegReg = MI->getOperand(Op+4);
149
150  // If this has a segment register, print it.
151  if (SegReg.getReg()) {
152    printOperand(MI, Op+4, O);
153    O << ':';
154  }
155
156  if (DispSpec.isImm()) {
157    int64_t DispVal = DispSpec.getImm();
158    if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
159      O << DispVal;
160  } else {
161    assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
162    O << *DispSpec.getExpr();
163  }
164
165  if (IndexReg.getReg() || BaseReg.getReg()) {
166    O << '(';
167    if (BaseReg.getReg())
168      printOperand(MI, Op, O);
169
170    if (IndexReg.getReg()) {
171      O << ',';
172      printOperand(MI, Op+2, O);
173      unsigned ScaleVal = MI->getOperand(Op+1).getImm();
174      if (ScaleVal != 1)
175        O << ',' << ScaleVal;
176    }
177    O << ')';
178  }
179}
180