1//===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file includes code for rendering MCInst instances as Intel-style
11// assembly.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "asm-printer"
16#include "X86IntelInstPrinter.h"
17#include "X86InstComments.h"
18#include "MCTargetDesc/X86BaseInfo.h"
19#include "MCTargetDesc/X86MCTargetDesc.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCExpr.h"
22#include "llvm/MC/MCInstrInfo.h"
23#include "llvm/Support/ErrorHandling.h"
24#include "llvm/Support/FormattedStream.h"
25#include <cctype>
26using namespace llvm;
27
28#include "X86GenAsmWriter1.inc"
29
30void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
31  OS << getRegisterName(RegNo);
32}
33
34void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
35                                    StringRef Annot) {
36  const MCInstrDesc &Desc = MII.get(MI->getOpcode());
37  uint64_t TSFlags = Desc.TSFlags;
38
39  if (TSFlags & X86II::LOCK)
40    OS << "\tlock\n";
41
42  printInstruction(MI, OS);
43
44  // Next always print the annotation.
45  printAnnotation(OS, Annot);
46
47  // If verbose assembly is enabled, we can print some informative comments.
48  if (CommentStream)
49    EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
50}
51
52void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
53                                     raw_ostream &O) {
54  switch (MI->getOperand(Op).getImm()) {
55  default: llvm_unreachable("Invalid ssecc argument!");
56  case    0: O << "eq"; break;
57  case    1: O << "lt"; break;
58  case    2: O << "le"; break;
59  case    3: O << "unord"; break;
60  case    4: O << "neq"; break;
61  case    5: O << "nlt"; break;
62  case    6: O << "nle"; break;
63  case    7: O << "ord"; break;
64  case    8: O << "eq_uq"; break;
65  case    9: O << "nge"; break;
66  case  0xa: O << "ngt"; break;
67  case  0xb: O << "false"; break;
68  case  0xc: O << "neq_oq"; break;
69  case  0xd: O << "ge"; break;
70  case  0xe: O << "gt"; break;
71  case  0xf: O << "true"; break;
72  case 0x10: O << "eq_os"; break;
73  case 0x11: O << "lt_oq"; break;
74  case 0x12: O << "le_oq"; break;
75  case 0x13: O << "unord_s"; break;
76  case 0x14: O << "neq_us"; break;
77  case 0x15: O << "nlt_uq"; break;
78  case 0x16: O << "nle_uq"; break;
79  case 0x17: O << "ord_s"; break;
80  case 0x18: O << "eq_us"; break;
81  case 0x19: O << "nge_uq"; break;
82  case 0x1a: O << "ngt_uq"; break;
83  case 0x1b: O << "false_os"; break;
84  case 0x1c: O << "neq_os"; break;
85  case 0x1d: O << "ge_oq"; break;
86  case 0x1e: O << "gt_oq"; break;
87  case 0x1f: O << "true_us"; break;
88
89  }
90}
91
92/// printPCRelImm - This is used to print an immediate value that ends up
93/// being encoded as a pc-relative value.
94void X86IntelInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
95                                        raw_ostream &O) {
96  const MCOperand &Op = MI->getOperand(OpNo);
97  if (Op.isImm())
98    O << Op.getImm();
99  else {
100    assert(Op.isExpr() && "unknown pcrel immediate operand");
101    // If a symbolic branch target was added as a constant expression then print
102    // that address in hex.
103    const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
104    int64_t Address;
105    if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
106      O << "0x";
107      O.write_hex(Address);
108    }
109    else {
110      // Otherwise, just print the expression.
111      O << *Op.getExpr();
112    }
113  }
114}
115
116static void PrintRegName(raw_ostream &O, StringRef RegName) {
117  for (unsigned i = 0, e = RegName.size(); i != e; ++i)
118    O << (char)toupper(RegName[i]);
119}
120
121void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
122                                       raw_ostream &O) {
123  const MCOperand &Op = MI->getOperand(OpNo);
124  if (Op.isReg()) {
125    PrintRegName(O, getRegisterName(Op.getReg()));
126  } else if (Op.isImm()) {
127    O << Op.getImm();
128  } else {
129    assert(Op.isExpr() && "unknown operand kind in printOperand");
130    O << *Op.getExpr();
131  }
132}
133
134void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
135                                            raw_ostream &O) {
136  const MCOperand &BaseReg  = MI->getOperand(Op);
137  unsigned ScaleVal         = MI->getOperand(Op+1).getImm();
138  const MCOperand &IndexReg = MI->getOperand(Op+2);
139  const MCOperand &DispSpec = MI->getOperand(Op+3);
140  const MCOperand &SegReg   = MI->getOperand(Op+4);
141
142  // If this has a segment register, print it.
143  if (SegReg.getReg()) {
144    printOperand(MI, Op+4, O);
145    O << ':';
146  }
147
148  O << '[';
149
150  bool NeedPlus = false;
151  if (BaseReg.getReg()) {
152    printOperand(MI, Op, O);
153    NeedPlus = true;
154  }
155
156  if (IndexReg.getReg()) {
157    if (NeedPlus) O << " + ";
158    if (ScaleVal != 1)
159      O << ScaleVal << '*';
160    printOperand(MI, Op+2, O);
161    NeedPlus = true;
162  }
163
164  if (!DispSpec.isImm()) {
165    if (NeedPlus) O << " + ";
166    assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
167    O << *DispSpec.getExpr();
168  } else {
169    int64_t DispVal = DispSpec.getImm();
170    if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
171      if (NeedPlus) {
172        if (DispVal > 0)
173          O << " + ";
174        else {
175          O << " - ";
176          DispVal = -DispVal;
177        }
178      }
179      O << DispVal;
180    }
181  }
182
183  O << ']';
184}
185