1//===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the PPCMCCodeEmitter class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mccodeemitter"
15#include "MCTargetDesc/PPCBaseInfo.h"
16#include "MCTargetDesc/PPCFixupKinds.h"
17#include "llvm/MC/MCCodeEmitter.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/ADT/Statistic.h"
20#include "llvm/Support/raw_ostream.h"
21#include "llvm/Support/ErrorHandling.h"
22using namespace llvm;
23
24STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
25
26namespace {
27class PPCMCCodeEmitter : public MCCodeEmitter {
28  PPCMCCodeEmitter(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION;
29  void operator=(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION;
30
31public:
32  PPCMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
33                   MCContext &ctx) {
34  }
35
36  ~PPCMCCodeEmitter() {}
37
38  unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
39                               SmallVectorImpl<MCFixup> &Fixups) const;
40  unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
41                             SmallVectorImpl<MCFixup> &Fixups) const;
42  unsigned getHA16Encoding(const MCInst &MI, unsigned OpNo,
43                           SmallVectorImpl<MCFixup> &Fixups) const;
44  unsigned getLO16Encoding(const MCInst &MI, unsigned OpNo,
45                           SmallVectorImpl<MCFixup> &Fixups) const;
46  unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
47                            SmallVectorImpl<MCFixup> &Fixups) const;
48  unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
49                             SmallVectorImpl<MCFixup> &Fixups) const;
50  unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
51                               SmallVectorImpl<MCFixup> &Fixups) const;
52
53  /// getMachineOpValue - Return binary encoding of operand. If the machine
54  /// operand requires relocation, record the relocation and return zero.
55  unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
56                             SmallVectorImpl<MCFixup> &Fixups) const;
57
58  // getBinaryCodeForInstr - TableGen'erated function for getting the
59  // binary encoding for an instruction.
60  uint64_t getBinaryCodeForInstr(const MCInst &MI,
61                                 SmallVectorImpl<MCFixup> &Fixups) const;
62  void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
63                         SmallVectorImpl<MCFixup> &Fixups) const {
64    unsigned Bits = getBinaryCodeForInstr(MI, Fixups);
65
66    // Output the constant in big endian byte order.
67    for (unsigned i = 0; i != 4; ++i) {
68      OS << (char)(Bits >> 24);
69      Bits <<= 8;
70    }
71
72    ++MCNumEmitted;  // Keep track of the # of mi's emitted.
73  }
74
75};
76
77} // end anonymous namespace
78
79MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
80                                            const MCRegisterInfo &MRI,
81                                            const MCSubtargetInfo &STI,
82                                            MCContext &Ctx) {
83  return new PPCMCCodeEmitter(MCII, STI, Ctx);
84}
85
86unsigned PPCMCCodeEmitter::
87getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
88                    SmallVectorImpl<MCFixup> &Fixups) const {
89  const MCOperand &MO = MI.getOperand(OpNo);
90  if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
91
92  // Add a fixup for the branch target.
93  Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
94                                   (MCFixupKind)PPC::fixup_ppc_br24));
95  return 0;
96}
97
98unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
99                                     SmallVectorImpl<MCFixup> &Fixups) const {
100  const MCOperand &MO = MI.getOperand(OpNo);
101  if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
102
103  // Add a fixup for the branch target.
104  Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
105                                   (MCFixupKind)PPC::fixup_ppc_brcond14));
106  return 0;
107}
108
109unsigned PPCMCCodeEmitter::getHA16Encoding(const MCInst &MI, unsigned OpNo,
110                                       SmallVectorImpl<MCFixup> &Fixups) const {
111  const MCOperand &MO = MI.getOperand(OpNo);
112  if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
113
114  // Add a fixup for the branch target.
115  Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
116                                   (MCFixupKind)PPC::fixup_ppc_ha16));
117  return 0;
118}
119
120unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo,
121                                       SmallVectorImpl<MCFixup> &Fixups) const {
122  const MCOperand &MO = MI.getOperand(OpNo);
123  if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
124
125  // Add a fixup for the branch target.
126  Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
127                                   (MCFixupKind)PPC::fixup_ppc_lo16));
128  return 0;
129}
130
131unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
132                                            SmallVectorImpl<MCFixup> &Fixups) const {
133  // Encode (imm, reg) as a memri, which has the low 16-bits as the
134  // displacement and the next 5 bits as the register #.
135  assert(MI.getOperand(OpNo+1).isReg());
136  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16;
137
138  const MCOperand &MO = MI.getOperand(OpNo);
139  if (MO.isImm())
140    return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
141
142  // Add a fixup for the displacement field.
143  Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
144                                   (MCFixupKind)PPC::fixup_ppc_lo16));
145  return RegBits;
146}
147
148
149unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
150                                       SmallVectorImpl<MCFixup> &Fixups) const {
151  // Encode (imm, reg) as a memrix, which has the low 14-bits as the
152  // displacement and the next 5 bits as the register #.
153  assert(MI.getOperand(OpNo+1).isReg());
154  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14;
155
156  const MCOperand &MO = MI.getOperand(OpNo);
157  if (MO.isImm())
158    return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits;
159
160  // Add a fixup for the branch target.
161  Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
162                                   (MCFixupKind)PPC::fixup_ppc_lo14));
163  return RegBits;
164}
165
166
167unsigned PPCMCCodeEmitter::
168get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
169                    SmallVectorImpl<MCFixup> &Fixups) const {
170  const MCOperand &MO = MI.getOperand(OpNo);
171  assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
172         (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
173  return 0x80 >> getPPCRegisterNumbering(MO.getReg());
174}
175
176
177unsigned PPCMCCodeEmitter::
178getMachineOpValue(const MCInst &MI, const MCOperand &MO,
179                  SmallVectorImpl<MCFixup> &Fixups) const {
180  if (MO.isReg()) {
181    // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
182    // The GPR operand should come through here though.
183    assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
184           MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
185    return getPPCRegisterNumbering(MO.getReg());
186  }
187
188  assert(MO.isImm() &&
189         "Relocation required in an instruction that we cannot encode!");
190  return MO.getImm();
191}
192
193
194#include "PPCGenMCCodeEmitter.inc"
195